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Review request for Default. Description ------- CPU: Round-two unifying instr/data CPU ports across models This patch continues the unification of how the different CPU models create and share their instruction and data ports. Most importantly, it forces every CPU to have an instruction and a data port, and gives these ports explicit getters in the BaseCPU (getDataPort and getInstPort). The patch helps in simplifying the code, make assumptions more explicit, andfurther ease future patches related to the CPU ports. The biggest changes are in the in-order model (that was not modified in the previous unification patch), which now moves the ports from the CacheUnit to the CPU. It also distinguishes the instruction fetch and load-store unit from the rest of the resources, and avoids the use of indices and casting in favour of keeping track of these two units explicitly (since they are always there anyways). The atomic, timing and O3 model simply return references to their already existing ports. Diffs ----- src/cpu/base.hh 2eaf1809c6c6 src/cpu/base.cc 2eaf1809c6c6 src/cpu/base_dyn_inst.hh 2eaf1809c6c6 src/cpu/inorder/InOrderCPU.py 2eaf1809c6c6 src/cpu/inorder/cpu.hh 2eaf1809c6c6 src/cpu/inorder/cpu.cc 2eaf1809c6c6 src/cpu/inorder/resource.hh 2eaf1809c6c6 src/cpu/inorder/resource_pool.hh 2eaf1809c6c6 src/cpu/inorder/resource_pool.cc 2eaf1809c6c6 src/cpu/inorder/resources/cache_unit.hh 2eaf1809c6c6 src/cpu/inorder/resources/cache_unit.cc 2eaf1809c6c6 src/cpu/o3/cpu.hh 2eaf1809c6c6 src/cpu/o3/cpu.cc 2eaf1809c6c6 src/cpu/o3/fetch_impl.hh 2eaf1809c6c6 src/cpu/o3/iew_impl.hh 2eaf1809c6c6 src/cpu/o3/lsq_impl.hh 2eaf1809c6c6 src/cpu/simple/atomic.hh 2eaf1809c6c6 src/cpu/simple/atomic.cc 2eaf1809c6c6 src/cpu/simple/base.hh 2eaf1809c6c6 src/cpu/simple/timing.hh 2eaf1809c6c6 src/cpu/simple/timing.cc 2eaf1809c6c6 src/cpu/thread_state.cc 2eaf1809c6c6 src/kern/tru64/tru64_events.cc 2eaf1809c6c6 src/mem/fs_translating_port_proxy.cc 2eaf1809c6c6 Diff: http://reviews.gem5.org/r/1046/diff/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
