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looks fine to me, but steve probably needs to take a look. - Ali Saidi On Feb. 21, 2012, 3:22 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1056/ > ----------------------------------------------------------- > > (Updated Feb. 21, 2012, 3:22 a.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Simplify cache ports preparing for master/slave split > > This patch splits the two cache ports into a master (memory-side) and > slave (cpu-side) subclass of port with slightly different > functionality. For example, it is only the CPU-side port that blocks > incoming requests, and only the memory-side port that schedules send > events outside of what the transmit list dictates. > > This patch simplifies the two classes by relying further on > SimpleTimingPort and also generalises the latter to better accommodate > the changes (introducing trySendTiming and scheduleSend). The > memory-side cache port overrides sendDeferredPacket to be able to not > only send responses from the transmit list, but also send requests > based on the MSHRs. > > A follow on patch further simplifies the SimpleTimingPort and the > cache ports. > > > Diffs > ----- > > src/mem/cache/base.hh 2629f0b99e8d > src/mem/cache/base.cc 2629f0b99e8d > src/mem/cache/cache.hh 2629f0b99e8d > src/mem/cache/cache_impl.hh 2629f0b99e8d > src/mem/tport.hh 2629f0b99e8d > src/mem/tport.cc 2629f0b99e8d > > Diff: http://reviews.gem5.org/r/1056/diff/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
