changeset 241ee47b0dc6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=241ee47b0dc6
description:
MEM: Simplify cache ports preparing for master/slave split
This patch splits the two cache ports into a master (memory-side) and
slave (cpu-side) subclass of port with slightly different
functionality. For example, it is only the CPU-side port that blocks
incoming requests, and only the memory-side port that schedules send
events outside of what the transmit list dictates.
This patch simplifies the two classes by relying further on
SimpleTimingPort and also generalises the latter to better accommodate
the changes (introducing trySendTiming and scheduleSend). The
memory-side cache port overrides sendDeferredPacket to be able to not
only send responses from the transmit list, but also send requests
based on the MSHRs.
A follow on patch further simplifies the SimpleTimingPort and the
cache ports.
diffstat:
src/mem/cache/base.cc | 76 ++++++++++-------------
src/mem/cache/base.hh | 96 +++++++++++++++++++++++-------
src/mem/cache/cache.hh | 74 +++++++++++++----------
src/mem/cache/cache_impl.hh | 139 +++++++++++++------------------------------
src/mem/tport.cc | 130 +++++++++++++++++++++++++---------------
src/mem/tport.hh | 49 +++++++++++++--
6 files changed, 313 insertions(+), 251 deletions(-)
diffs (truncated from 919 to 300 lines):
diff -r 74490e94da0c -r 241ee47b0dc6 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Fri Feb 24 11:50:15 2012 -0500
+++ b/src/mem/cache/base.cc Fri Feb 24 11:52:49 2012 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -42,13 +54,20 @@
using namespace std;
-BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
- const std::string &_label)
- : SimpleTimingPort(_name, _cache), cache(_cache),
- label(_label), blocked(false), mustSendRetry(false)
+BaseCache::CacheMasterPort::CacheMasterPort(const std::string &_name,
+ BaseCache *_cache,
+ const std::string &_label)
+ : SimpleTimingPort(_name, _cache, _label)
{
}
+BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
+ BaseCache *_cache,
+ const std::string &_label)
+ : SimpleTimingPort(_name, _cache, _label), blocked(false),
+ mustSendRetry(false), sendRetryEvent(this)
+{
+}
BaseCache::BaseCache(const Params *p)
: MemObject(p),
@@ -69,56 +88,25 @@
{
}
-
-bool
-BaseCache::CachePort::checkFunctional(PacketPtr pkt)
-{
- pkt->pushLabel(label);
- bool done = SimpleTimingPort::checkFunctional(pkt);
- pkt->popLabel();
- return done;
-}
-
-
-unsigned
-BaseCache::CachePort::deviceBlockSize() const
-{
- return cache->getBlockSize();
-}
-
-
-bool
-BaseCache::CachePort::recvRetryCommon()
-{
- assert(waitingOnRetry);
- waitingOnRetry = false;
- return false;
-}
-
-
void
-BaseCache::CachePort::setBlocked()
+BaseCache::CacheSlavePort::setBlocked()
{
assert(!blocked);
- DPRINTF(Cache, "Cache Blocking\n");
+ DPRINTF(CachePort, "Cache port %s blocking new requests\n", name());
blocked = true;
- //Clear the retry flag
- mustSendRetry = false;
}
void
-BaseCache::CachePort::clearBlocked()
+BaseCache::CacheSlavePort::clearBlocked()
{
assert(blocked);
- DPRINTF(Cache, "Cache Unblocking\n");
+ DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
blocked = false;
- if (mustSendRetry)
- {
- DPRINTF(Cache, "Cache Sending Retry\n");
+ if (mustSendRetry) {
+ DPRINTF(CachePort, "Cache port %s sending retry\n", name());
mustSendRetry = false;
- SendRetryEvent *ev = new SendRetryEvent(this, true);
// @TODO: need to find a better time (next bus cycle?)
- cache->schedule(ev, curTick() + 1);
+ owner->schedule(sendRetryEvent, curTick() + 1);
}
}
@@ -126,8 +114,8 @@
void
BaseCache::init()
{
- if (!cpuSidePort || !memSidePort)
- panic("Cache not hooked up on both sides\n");
+ if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
+ panic("Cache %s not hooked up on both sides\n", name());
cpuSidePort->sendRangeChange();
}
diff -r 74490e94da0c -r 241ee47b0dc6 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Fri Feb 24 11:50:15 2012 -0500
+++ b/src/mem/cache/base.hh Fri Feb 24 11:52:49 2012 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -97,50 +109,88 @@
protected:
- class CachePort : public SimpleTimingPort
+ /**
+ * A cache master port is used for the memory-side port of the
+ * cache, and in addition to the basic timing port that only sends
+ * response packets through a transmit list, it also offers the
+ * ability to schedule and send request packets (requests &
+ * writebacks). The send event is scheduled through requestBus,
+ * and the sendDeferredPacket of the timing port is modified to
+ * consider both the transmit list and the requests from the MSHR.
+ */
+ class CacheMasterPort : public SimpleTimingPort
{
+
public:
- BaseCache *cache;
+
+ /**
+ * Schedule a send of a request packet (from the MSHR). Note
+ * that we could already have a retry or a transmit list of
+ * responses outstanding.
+ */
+ void requestBus(RequestCause cause, Tick time)
+ {
+ DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
+ schedSendEvent(time);
+ }
+
+ void respond(PacketPtr pkt, Tick time) {
+ schedSendTiming(pkt, time);
+ }
protected:
- CachePort(const std::string &_name, BaseCache *_cache,
- const std::string &_label);
- virtual unsigned deviceBlockSize() const;
+ CacheMasterPort(const std::string &_name, BaseCache *_cache,
+ const std::string &_label);
- bool recvRetryCommon();
+ /**
+ * Memory-side port always snoops.
+ *
+ * return always true
+ */
+ virtual bool isSnooping() { return true; }
+ };
- typedef EventWrapper<Port, &Port::sendRetry>
- SendRetryEvent;
-
- const std::string label;
+ /**
+ * A cache slave port is used for the CPU-side port of the cache,
+ * and it is basically a simple timing port that uses a transmit
+ * list for responses to the CPU (or connected master). In
+ * addition, it has the functionality to block the port for
+ * incoming requests. If blocked, the port will issue a retry once
+ * unblocked.
+ */
+ class CacheSlavePort : public SimpleTimingPort
+ {
public:
+
+ /** Do not accept any new requests. */
void setBlocked();
+ /** Return to normal operation and accept new requests. */
void clearBlocked();
- bool checkFunctional(PacketPtr pkt);
+ void respond(PacketPtr pkt, Tick time) {
+ schedSendTiming(pkt, time);
+ }
+
+ protected:
+
+ CacheSlavePort(const std::string &_name, BaseCache *_cache,
+ const std::string &_label);
bool blocked;
bool mustSendRetry;
- void requestBus(RequestCause cause, Tick time)
- {
- DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
- if (!waitingOnRetry) {
- schedSendEvent(time);
- }
- }
+ private:
- void respond(PacketPtr pkt, Tick time) {
- schedSendTiming(pkt, time);
- }
+ EventWrapper<Port, &Port::sendRetry> sendRetryEvent;
+
};
- CachePort *cpuSidePort;
- CachePort *memSidePort;
+ CacheSlavePort *cpuSidePort;
+ CacheMasterPort *memSidePort;
protected:
diff -r 74490e94da0c -r 241ee47b0dc6 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Fri Feb 24 11:50:15 2012 -0500
+++ b/src/mem/cache/cache.hh Fri Feb 24 11:52:49 2012 -0500
@@ -41,6 +41,7 @@
* Dave Greene
* Steve Reinhardt
* Ron Dreslinski
+ * Andreas Hansson
*/
/**
@@ -76,59 +77,68 @@
protected:
- class CpuSidePort : public CachePort
+ /**
+ * The CPU-side port extends the base cache slave port with access
+ * functions for functional, atomic and timing requests.
+ */
+ class CpuSidePort : public CacheSlavePort
{
- public:
- CpuSidePort(const std::string &_name,
- Cache<TagStore> *_cache,
- const std::string &_label);
+ private:
- // BaseCache::CachePort just has a BaseCache *; this function
- // lets us get back the type info we lost when we stored the
- // cache pointer there.
- Cache<TagStore> *myCache() {
- return static_cast<Cache<TagStore> *>(cache);
- }
+ // a pointer to our specific cache implementation
+ Cache<TagStore> *cache;
- virtual AddrRangeList getAddrRanges();
+ protected:
virtual bool recvTiming(PacketPtr pkt);
virtual Tick recvAtomic(PacketPtr pkt);
virtual void recvFunctional(PacketPtr pkt);
+
+ virtual unsigned deviceBlockSize() const
+ { return cache->getBlockSize(); }
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