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Review request for Default. Description ------- CPU: Fix switching in of x86 CPU with interrupt and TLB ports This patch fixes the, currently broken, switching of CPUs for x86 by ensuring that the interrupt device does not initialise the ports if the CPU is not connected, and also ensures that the TLB walker ports of the new CPU are actually connected. To do the latter the getPort of the TLB and TLB walker for x86 were added to override the BaseTLB that returns NULL. Diffs ----- src/arch/alpha/interrupts.hh 241ee47b0dc6 src/arch/arm/interrupts.hh 241ee47b0dc6 src/arch/mips/interrupts.hh 241ee47b0dc6 src/arch/power/interrupts.hh 241ee47b0dc6 src/arch/sparc/interrupts.hh 241ee47b0dc6 src/arch/x86/interrupts.hh 241ee47b0dc6 src/arch/x86/interrupts.cc 241ee47b0dc6 src/arch/x86/pagetable_walker.hh 241ee47b0dc6 src/arch/x86/tlb.hh 241ee47b0dc6 src/arch/x86/tlb.cc 241ee47b0dc6 src/cpu/base.cc 241ee47b0dc6 Diff: http://reviews.gem5.org/r/1062/diff/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
