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Review request for Default. Description ------- MEM: Split SimpleTimingPort into PacketQueue and ports This patch decouples the queueing and the port interactions to simplify the introduction of the master and slave ports. By separating the queueing functionality from the port itself, it becomes much easier to distinguish between master and slave ports, and still retain the queueing ability for both (without code duplication). As part of the split into a PacketQueue and a port, there is now also a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The QueuedPort is useful for ports that want to leave the packet transmission of outgoing packets to the queue and is used by both master and slave ports. The SimpleTimingPort inherits from the QueuedPort and adds the implemention of recvTiming and recvFunctional through recvAtomic. The PioPort and MessagePort are cleaned up as part of the changes. Diffs ----- src/dev/io_device.hh c68ae0f78d8e src/dev/io_device.cc c68ae0f78d8e src/dev/x86/intdev.cc c68ae0f78d8e src/mem/SConscript c68ae0f78d8e src/mem/cache/base.hh c68ae0f78d8e src/mem/cache/base.cc c68ae0f78d8e src/mem/cache/cache.hh c68ae0f78d8e src/mem/cache/cache_impl.hh c68ae0f78d8e src/mem/mport.hh c68ae0f78d8e src/mem/packet_queue.hh PRE-CREATION src/mem/packet_queue.cc PRE-CREATION src/mem/physical.cc c68ae0f78d8e src/mem/qport.hh PRE-CREATION src/mem/ruby/system/RubyPort.hh c68ae0f78d8e src/mem/ruby/system/RubyPort.cc c68ae0f78d8e src/mem/tport.hh c68ae0f78d8e src/mem/tport.cc c68ae0f78d8e Diff: http://reviews.gem5.org/r/1064/diff/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
