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Ship it! Ship It! - Steve Reinhardt On March 9, 2012, 7:17 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1064/ > ----------------------------------------------------------- > > (Updated March 9, 2012, 7:17 a.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Split SimpleTimingPort into PacketQueue and ports > > This patch decouples the queueing and the port interactions to > simplify the introduction of the master and slave ports. By separating > the queueing functionality from the port itself, it becomes much > easier to distinguish between master and slave ports, and still retain > the queueing ability for both (without code duplication). > > As part of the split into a PacketQueue and a port, there is now also > a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The > QueuedPort is useful for ports that want to leave the packet > transmission of outgoing packets to the queue and is used by both > master and slave ports. The SimpleTimingPort inherits from the > QueuedPort and adds the implemention of recvTiming and recvFunctional > through recvAtomic. > > The PioPort and MessagePort are cleaned up as part of the changes. > > > Diffs > ----- > > src/dev/io_device.hh b4249e884de4 > src/dev/io_device.cc b4249e884de4 > src/dev/x86/intdev.cc b4249e884de4 > src/mem/SConscript b4249e884de4 > src/mem/cache/base.hh b4249e884de4 > src/mem/cache/base.cc b4249e884de4 > src/mem/cache/cache.hh b4249e884de4 > src/mem/cache/cache_impl.hh b4249e884de4 > src/mem/mport.hh b4249e884de4 > src/mem/packet_queue.hh PRE-CREATION > src/mem/packet_queue.cc PRE-CREATION > src/mem/physical.cc b4249e884de4 > src/mem/qport.hh PRE-CREATION > src/mem/ruby/system/RubyPort.hh b4249e884de4 > src/mem/ruby/system/RubyPort.cc b4249e884de4 > src/mem/tport.hh b4249e884de4 > src/mem/tport.cc b4249e884de4 > > Diff: http://reviews.gem5.org/r/1064/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
