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I would suggest to keep it uniform and rely on Ruby if possible. How come we cannot simply use the cpu sequencers master/slave port (they are vector ports)? - Andreas Hansson On March 5, 2012, 3:46 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1079/ > ----------------------------------------------------------- > > (Updated March 5, 2012, 3:46 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8880:97c5fbb8d063 > --------------------------- > se.py: Changes to ruby portion due to SE/FS merge > With the SE/FS merge, interrupt controller is created irrespective of the > mode. Since interrupts do not go through the Ruby memory system, a separate > bus is required for the interrupt controller and the devices. This patch > creates the piobus and the interrupt controller in SE mode for Ruby. > > > Diffs > ----- > > configs/example/se.py 347fc850752c > > Diff: http://reviews.gem5.org/r/1079/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
