> On March 6, 2012, 12:39 a.m., Andreas Hansson wrote:
> > I would suggest to keep it uniform and rely on Ruby if possible. How come
> > we cannot simply use the cpu sequencers master/slave port (they are vector
> > ports)?
>
> Nilay Vaish wrote:
> Andreas, can you ask your question in more detail?
Why does it not say:
system.cpu[i].createInterruptController()
system.cpu[i].interrupts.pio = system.ruby._cpu_ruby_ports[i].master
system.cpu[i].interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
system.cpu[i].interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
- Andreas
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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1079/#review2276
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On March 5, 2012, 3:46 p.m., Nilay Vaish wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1079/
> -----------------------------------------------------------
>
> (Updated March 5, 2012, 3:46 p.m.)
>
>
> Review request for Default.
>
>
> Description
> -------
>
> Changeset 8880:97c5fbb8d063
> ---------------------------
> se.py: Changes to ruby portion due to SE/FS merge
> With the SE/FS merge, interrupt controller is created irrespective of the
> mode. Since interrupts do not go through the Ruby memory system, a separate
> bus is required for the interrupt controller and the devices. This patch
> creates the piobus and the interrupt controller in SE mode for Ruby.
>
>
> Diffs
> -----
>
> configs/example/se.py 347fc850752c
>
> Diff: http://reviews.gem5.org/r/1079/diff/
>
>
> Testing
> -------
>
>
> Thanks,
>
> Nilay Vaish
>
>
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