changeset 20ea02da9c53 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=20ea02da9c53
description:
CheckerCPU: Make CheckerCPU runtime selectable instead of compile
selectable
Enables the CheckerCPU to be selected at runtime with the --checker
option
from the configs/example/fs.py and configs/example/se.py configuration
files. Also merges with the SE/FS changes.
diffstat:
SConstruct | 3 +-
configs/common/Options.py | 1 +
configs/common/Simulation.py | 8 +++++
configs/example/fs.py | 6 ++-
configs/example/se.py | 21 ++++++++------
src/arch/SConscript | 3 +-
src/arch/arm/isa.cc | 51 ++++++++++++++---------------------
src/arch/arm/utility.cc | 14 +++++----
src/cpu/BaseCPU.py | 6 +++-
src/cpu/SConscript | 30 ++++-----------------
src/cpu/base.cc | 55 +++++++++++++++++---------------------
src/cpu/base_dyn_inst.hh | 26 +++++++++---------
src/cpu/base_dyn_inst_impl.hh | 5 ---
src/cpu/checker/cpu.cc | 25 +++++++++-------
src/cpu/checker/cpu.hh | 27 +++++++++++++++---
src/cpu/checker/cpu_impl.hh | 13 +++++---
src/cpu/checker/thread_context.hh | 6 ++-
src/cpu/dummy_checker_builder.cc | 1 +
src/cpu/o3/O3CPU.py | 32 +++++++++++-----------
src/cpu/o3/SConscript | 5 +--
src/cpu/o3/checker_builder.cc | 1 +
src/cpu/o3/commit_impl.hh | 12 +-------
src/cpu/o3/cpu.cc | 16 ++--------
src/cpu/o3/cpu.hh | 3 --
src/cpu/o3/cpu_builder.cc | 1 -
src/cpu/o3/dyn_inst_impl.hh | 10 +++---
src/cpu/o3/fetch_impl.hh | 6 +---
src/cpu/o3/iew_impl.hh | 12 ++------
src/cpu/o3/lsq_unit_impl.hh | 21 +++++---------
src/cpu/o3/thread_context.hh | 7 +----
src/cpu/o3/thread_context_impl.hh | 3 --
src/cpu/ozone/OzoneCPU.py | 11 +++----
src/cpu/ozone/SConscript | 5 +--
src/cpu/ozone/cpu_impl.hh | 13 +-------
src/cpu/ozone/front_end_impl.hh | 8 +----
src/cpu/ozone/lw_back_end_impl.hh | 10 +------
src/cpu/ozone/lw_lsq_impl.hh | 7 ----
src/cpu/simple/BaseSimpleCPU.py | 18 +++++++----
src/cpu/simple/base.cc | 10 +-----
src/cpu/simple/base.hh | 9 +----
src/cpu/simple_thread.hh | 9 +----
src/cpu/thread_context.hh | 14 ++-------
42 files changed, 227 insertions(+), 317 deletions(-)
diffs (truncated from 1610 to 300 lines):
diff -r 5e8d2d7162b0 -r 20ea02da9c53 SConstruct
--- a/SConstruct Fri Mar 09 09:59:26 2012 -0500
+++ b/SConstruct Fri Mar 09 09:59:27 2012 -0500
@@ -845,13 +845,12 @@
False),
BoolVariable('USE_POSIX_CLOCK', 'Use POSIX Clocks', have_posix_clock),
BoolVariable('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv),
- BoolVariable('USE_CHECKER', 'Use checker for detailed CPU models', False),
BoolVariable('CP_ANNOTATE', 'Enable critical path annotation capability',
False),
)
# These variables get exported to #defines in config/*.hh (see src/SConscript).
export_vars += ['USE_FENV', 'NO_FAST_ALLOC', 'FORCE_FAST_ALLOC',
- 'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP', 'USE_CHECKER',
+ 'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP',
'TARGET_ISA', 'CP_ANNOTATE', 'USE_POSIX_CLOCK' ]
###################################################
diff -r 5e8d2d7162b0 -r 20ea02da9c53 configs/common/Options.py
--- a/configs/common/Options.py Fri Mar 09 09:59:26 2012 -0500
+++ b/configs/common/Options.py Fri Mar 09 09:59:27 2012 -0500
@@ -31,6 +31,7 @@
choices = ["atomic", "timing", "detailed", "inorder",
"arm_detailed"],
help = "type of cpu to run with")
+parser.add_option("--checker", action="store_true");
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
diff -r 5e8d2d7162b0 -r 20ea02da9c53 configs/common/Simulation.py
--- a/configs/common/Simulation.py Fri Mar 09 09:59:26 2012 -0500
+++ b/configs/common/Simulation.py Fri Mar 09 09:59:27 2012 -0500
@@ -129,6 +129,9 @@
# simulation period
if options.maxinsts:
switch_cpus[i].max_insts_any_thread = options.maxinsts
+ # Add checker cpu if selected
+ if options.checker:
+ switch_cpus[i].addCheckerCpu()
testsys.switch_cpus = switch_cpus
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
@@ -176,6 +179,11 @@
if options.maxinsts:
switch_cpus_1[i].max_insts_any_thread = options.maxinsts
+ # attach the checker cpu if selected
+ if options.checker:
+ switch_cpus[i].addCheckerCpu()
+ switch_cpus_1[i].addCheckerCpu()
+
testsys.switch_cpus = switch_cpus
testsys.switch_cpus_1 = switch_cpus_1
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
diff -r 5e8d2d7162b0 -r 20ea02da9c53 configs/example/fs.py
--- a/configs/example/fs.py Fri Mar 09 09:59:26 2012 -0500
+++ b/configs/example/fs.py Fri Mar 09 09:59:27 2012 -0500
@@ -152,8 +152,6 @@
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
-CacheConfig.config_cache(options, test_sys)
-
if bm[0]:
mem_size = bm[0].mem()
else:
@@ -171,6 +169,10 @@
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].physmem_port = test_sys.physmem.port
+ if options.checker:
+ test_sys.cpu[i].addCheckerCpu()
+
+CacheConfig.config_cache(options, test_sys)
if buildEnv['TARGET_ISA'] == 'mips':
setMipsOptions(TestCPUClass)
diff -r 5e8d2d7162b0 -r 20ea02da9c53 configs/example/se.py
--- a/configs/example/se.py Fri Mar 09 09:59:26 2012 -0500
+++ b/configs/example/se.py Fri Mar 09 09:59:27 2012 -0500
@@ -175,15 +175,6 @@
physmem = PhysicalMemory(range=AddrRange("512MB")),
membus = Bus(), mem_mode = test_mem_mode)
-if options.ruby:
- options.use_map = True
- Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-else:
- system.system_port = system.membus.slave
- system.physmem.port = system.membus.master
- CacheConfig.config_cache(options, system)
-
for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
@@ -194,6 +185,18 @@
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
+ if options.checker:
+ system.cpu[i].addCheckerCpu()
+
+if options.ruby:
+ options.use_map = True
+ Ruby.create_system(options, system)
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+else:
+ system.system_port = system.membus.slave
+ system.physmem.port = system.membus.master
+ CacheConfig.config_cache(options, system)
+
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
diff -r 5e8d2d7162b0 -r 20ea02da9c53 src/arch/SConscript
--- a/src/arch/SConscript Fri Mar 09 09:59:26 2012 -0500
+++ b/src/arch/SConscript Fri Mar 09 09:59:27 2012 -0500
@@ -94,8 +94,7 @@
# autogenerated files as targets and isa parser itself as a source.
def isa_desc_emitter(target, source, env):
cpu_models = list(env['CPU_MODELS'])
- if env['USE_CHECKER']:
- cpu_models.append('CheckerCPU')
+ cpu_models.append('CheckerCPU')
# Several files are generated from the ISA description.
# We always get the basic decoder and header file.
diff -r 5e8d2d7162b0 -r 20ea02da9c53 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Fri Mar 09 09:59:26 2012 -0500
+++ b/src/arch/arm/isa.cc Fri Mar 09 09:59:27 2012 -0500
@@ -39,17 +39,13 @@
*/
#include "arch/arm/isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
namespace ArmISA
{
@@ -294,11 +290,15 @@
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
-#if USE_CHECKER
- tc->pcStateNoRecord(pc);
-#else
- tc->pcState(pc);
-#endif //USE_CHECKER
+
+ // Follow slightly different semantics if a CheckerCPU object
+ // is connected
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ tc->pcStateNoRecord(pc);
+ } else {
+ tc->pcState(pc);
+ }
} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
misc_reg < MISCREG_CP15_END) {
panic("Unimplemented CP15 register %s wrote with %#x.\n",
@@ -401,14 +401,13 @@
oc = sys->getThreadContext(x);
oc->getDTBPtr()->allCpusCaching();
oc->getITBPtr()->allCpusCaching();
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ // If CheckerCPU is connected, need to notify it.
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getDTBPtr()->allCpusCaching();
checker->getITBPtr()->allCpusCaching();
}
-#endif
}
return;
}
@@ -426,14 +425,13 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAll();
oc->getDTBPtr()->flushAll();
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ // If CheckerCPU is connected, need to notify it of a flush
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushAll();
checker->getDTBPtr()->flushAll();
}
-#endif
}
return;
case MISCREG_ITLBIALL:
@@ -452,16 +450,14 @@
bits(newVal, 7,0));
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
}
-#endif
}
return;
case MISCREG_TLBIASIDIS:
@@ -472,14 +468,11 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
}
-#endif
}
return;
case MISCREG_TLBIMVAAIS:
@@ -490,14 +483,12 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
}
-#endif
}
return;
case MISCREG_ITLBIMVA:
diff -r 5e8d2d7162b0 -r 20ea02da9c53 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Fri Mar 09 09:59:26 2012 -0500
+++ b/src/arch/arm/utility.cc Fri Mar 09 09:59:27 2012 -0500
@@ -43,7 +43,7 @@
#include "arch/arm/tlb.hh"
#include "arch/arm/utility.hh"
#include "arch/arm/vtophys.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/fs_translating_port_proxy.hh"
@@ -118,11 +118,13 @@
{
TheISA::PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
-#if USE_CHECKER
- tc->pcStateNoRecord(newPC);
-#else
- tc->pcState(newPC);
-#endif
+
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ tc->pcStateNoRecord(newPC);
+ } else {
+ tc->pcState(newPC);
+ }
}
void
diff -r 5e8d2d7162b0 -r 20ea02da9c53 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Fri Mar 09 09:59:26 2012 -0500
+++ b/src/cpu/BaseCPU.py Fri Mar 09 09:59:27 2012 -0500
@@ -214,9 +214,10 @@
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+
# Checker doesn't need its own tlb caches because it does
# functional accesses only
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