changeset befcf4d79fc1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=befcf4d79fc1
description:
CheckerCPU: Add function stubs to non-ARM ISA source to compile with
CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be
compatible
with ISAs other than ARM. This patch adds the appropriate function
stubs to allow compilation.
diffstat:
src/arch/alpha/tlb.cc | 7 +++++++
src/arch/alpha/tlb.hh | 4 ++++
src/arch/mips/tlb.cc | 7 +++++++
src/arch/mips/tlb.hh | 5 +++++
src/arch/power/tlb.cc | 7 +++++++
src/arch/power/tlb.hh | 4 ++++
src/arch/sparc/tlb.cc | 7 +++++++
src/arch/sparc/tlb.hh | 4 ++++
src/arch/x86/tlb.cc | 7 +++++++
src/arch/x86/tlb.hh | 4 ++++
src/cpu/checker/cpu.hh | 14 ++++++++++++++
src/cpu/checker/cpu_impl.hh | 17 ++++++++++++-----
src/cpu/inorder/thread_context.hh | 13 +++++++++++++
13 files changed, 95 insertions(+), 5 deletions(-)
diffs (265 lines):
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/alpha/tlb.cc Fri Mar 09 09:59:28 2012 -0500
@@ -600,6 +600,13 @@
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
} // namespace AlphaISA
AlphaISA::TLB *
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/alpha/tlb.hh Fri Mar 09 09:59:28 2012 -0500
@@ -144,6 +144,10 @@
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /**
+ * translateFunctional stub function for future CheckerCPU support
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
};
} // namespace AlphaISA
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/mips/tlb.cc Fri Mar 09 09:59:28 2012 -0500
@@ -339,6 +339,13 @@
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
MipsISA::PTE &
TLB::index(bool advance)
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/mips/tlb.hh Fri Mar 09 09:59:28 2012 -0500
@@ -114,6 +114,11 @@
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /** Function stub for CheckerCPU compilation issues. MIPS does not
+ * support the Checker model at the moment.
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
+
private:
Fault translateInst(RequestPtr req, ThreadContext *tc);
Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/power/tlb.cc
--- a/src/arch/power/tlb.cc Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/power/tlb.cc Fri Mar 09 09:59:28 2012 -0500
@@ -326,6 +326,13 @@
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
PowerISA::PTE &
TLB::index(bool advance)
{
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/power/tlb.hh
--- a/src/arch/power/tlb.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/power/tlb.hh Fri Mar 09 09:59:28 2012 -0500
@@ -160,6 +160,10 @@
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /** Stub function for CheckerCPU compilation support. Power ISA not
+ * supported by Checker at the moment
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
// Checkpointing
void serialize(std::ostream &os);
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/sparc/tlb.cc Fri Mar 09 09:59:28 2012 -0500
@@ -841,6 +841,13 @@
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/sparc/tlb.hh Fri Mar 09 09:59:28 2012 -0500
@@ -164,6 +164,10 @@
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /** Stub function for compilation support with CheckerCPU. SPARC ISA
+ * does not support the Checker model at the moment
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/x86/tlb.cc Fri Mar 09 09:59:28 2012 -0500
@@ -405,6 +405,13 @@
translation->finish(fault, req, tc, mode);
}
+Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ panic("Not implemented\n");
+ return NoFault;
+}
+
Walker *
TLB::getWalker()
{
diff -r 20ea02da9c53 -r befcf4d79fc1 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/arch/x86/tlb.hh Fri Mar 09 09:59:28 2012 -0500
@@ -114,6 +114,10 @@
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ /** Stub function for compilation support of CheckerCPU. x86 ISA does
+ * not support Checker model at the moment
+ */
+ Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode
mode);
TlbEntry * insert(Addr vpn, TlbEntry &entry);
diff -r 20ea02da9c53 -r befcf4d79fc1 src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/cpu/checker/cpu.hh Fri Mar 09 09:59:28 2012 -0500
@@ -311,6 +311,20 @@
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscReg(reg_idx, val);
}
+
+#if THE_ISA == MIPS_ISA
+ uint64_t readRegOtherThread(int misc_reg)
+ {
+ panic("MIPS MT not defined for CheckerCPU.\n");
+ return 0;
+ }
+
+ void setRegOtherThread(int misc_reg, const TheISA::MiscReg &val)
+ {
+ panic("MIPS MT not defined for CheckerCPU.\n");
+ }
+#endif
+
/////////////////////////////////////////
void recordPCChange(const TheISA::PCState &val)
diff -r 20ea02da9c53 -r befcf4d79fc1 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/cpu/checker/cpu_impl.hh Fri Mar 09 09:59:28 2012 -0500
@@ -44,6 +44,7 @@
#include <list>
#include <string>
+#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "config/the_isa.hh"
@@ -201,9 +202,9 @@
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
-#ifdef TARGET_ALPHA
- thread->setFloatRegDouble(ZeroReg, 0.0);
-#endif // TARGET_ALPHA
+#if THE_ISA == ALPHA_ISA
+ thread->setFloatReg(ZeroReg, 0.0);
+#endif
// Check if any recent PC changes match up with anything we
// expect to happen. This is mostly to check if traps or
@@ -320,7 +321,9 @@
thread->pcState(pcState);
instPtr = thread->decoder.decode(newMachInst,
pcState.instAddr());
- machInst = newMachInst;
+#if THE_ISA != X86_ISA
+ machInst = newMachInst;
+#endif
} else {
fetchDone = false;
fetchOffset += sizeof(TheISA::MachInst);
@@ -476,7 +479,11 @@
}
}
- MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
+
+ MachInst mi;
+#if THE_ISA != X86_ISA
+ mi = static_cast<MachInst>(inst->staticInst->machInst);
+#endif
if (mi != machInst) {
panic("%lli: Binary instructions do not match! Inst: %#x, "
diff -r 20ea02da9c53 -r befcf4d79fc1 src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh Fri Mar 09 09:59:27 2012 -0500
+++ b/src/cpu/inorder/thread_context.hh Fri Mar 09 09:59:28 2012 -0500
@@ -40,6 +40,7 @@
#include "arch/kernel_stats.hh"
class EndQuiesceEvent;
+class CheckerCPU;
namespace Kernel {
class Statistics;
};
@@ -76,6 +77,12 @@
/** @TODO: PERF: Should we bind this to a pointer in constructor? */
TheISA::TLB *getDTBPtr() { return cpu->getDTBPtr(); }
+ /** Currently InOrder model does not support CheckerCPU, this is
+ * merely here for supporting compilation of gem5 with the Checker
+ * as a runtime option
+ */
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
+
Decoder *getDecoderPtr() { return cpu->getDecoderPtr(); }
System *getSystemPtr() { return cpu->system; }
@@ -215,6 +222,12 @@
void pcState(const TheISA::PCState &val)
{ cpu->pcState(val, thread->threadId()); }
+ /** Needs to be implemented for future CheckerCPU support.
+ * See O3CPU for examples on how to integrate Checker.
+ */
+ void pcStateNoRecord(const TheISA::PCState &val)
+ {}
+
Addr instAddr()
{ return cpu->instAddr(thread->threadId()); }
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