changeset 02b0b6b4d7c0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=02b0b6b4d7c0
description:
ARM: Fix branch prediction issue with CB(N)Z instruction
diffstat:
src/arch/arm/isa/templates/branch.isa | 11 +++--------
1 files changed, 3 insertions(+), 8 deletions(-)
diffs (28 lines):
diff -r b4249e884de4 -r 02b0b6b4d7c0 src/arch/arm/isa/templates/branch.isa
--- a/src/arch/arm/isa/templates/branch.isa Fri Mar 09 09:59:29 2012 -0500
+++ b/src/arch/arm/isa/templates/branch.isa Fri Mar 09 15:32:41 2012 -0500
@@ -212,6 +212,8 @@
};
}};
+// Only used by CBNZ, CBZ which is conditional based on
+// a register value even though the instruction is always unconditional.
def template BranchImmRegConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
int32_t _imm,
@@ -219,14 +221,7 @@
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
%(constructor)s;
- if (!(condCode == COND_AL || condCode == COND_UC)) {
- for (int x = 0; x < _numDestRegs; x++) {
- _srcRegIdx[_numSrcRegs++] = _destRegIdx[x];
- }
- flags[IsCondControl] = true;
- } else {
- flags[IsUncondControl] = true;
- }
+ flags[IsCondControl] = true;
}
}};
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