changeset e29c604a2582 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e29c604a2582 description: ARM: Update stats for CBNZ fix.
diffstat: tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout | 12 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 1358 ++-- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout | 12 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 2586 ++++----- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status | 2 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 6 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout | 12 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1332 ++-- tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 962 +- tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1010 +- tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr | 1 + tests/long/se/20.parser/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1108 ++-- tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/20.parser/ref/arm/linux/simple-timing/simout | 4 +- tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/30.eon/ref/arm/linux/o3-timing/simout | 8 +- tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1048 ++-- tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1088 ++-- tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1096 ++-- tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr | 1 + tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 968 +- tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini | 28 +- tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 990 +- tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt | 12 +- tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini | 28 +- tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt | 12 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt | 14 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt | 12 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt | 14 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt | 12 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status | 2 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout | 4 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | 10 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini | 28 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout | 4 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 10 +- tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini | 2 +- tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout | 6 +- tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt | 10 +- tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini | 15 +- tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout | 4 +- tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt | 10 +- tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini | 28 +- tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout | 4 +- tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt | 10 +- 86 files changed, 7323 insertions(+), 7282 deletions(-) diffs (truncated from 18391 to 300 lines): diff -r 02b0b6b4d7c0 -r e29c604a2582 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout Fri Mar 09 15:32:41 2012 -0500 +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout Fri Mar 09 15:33:07 2012 -0500 @@ -1,15 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 9 2012 08:32:03 -gem5 started Mar 9 2012 08:34:27 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker +gem5 compiled Mar 9 2012 10:15:20 +gem5 started Mar 9 2012 10:47:04 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker The currently selected ARM platforms doesn't support the amount of DRAM you've selected. Please try another platform Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503289265500 because m5_exit instruction encountered +Exiting @ tick 2503099557500 because m5_exit instruction encountered diff -r 02b0b6b4d7c0 -r e29c604a2582 tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt Fri Mar 09 15:32:41 2012 -0500 +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt Fri Mar 09 15:33:07 2012 -0500 @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503289 # Number of seconds simulated -sim_ticks 2503289265500 # Number of ticks simulated -final_tick 2503289265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503100 # Number of seconds simulated +sim_ticks 2503099557500 # Number of ticks simulated +final_tick 2503099557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55466 # Simulator instruction rate (inst/s) -host_op_rate 71644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2335415954 # Simulator tick rate (ticks/s) -host_mem_usage 389340 # Number of bytes of host memory used -host_seconds 1071.88 # Real time elapsed on the host -sim_insts 59452703 # Number of instructions simulated -sim_ops 76793713 # Number of ops (including micro ops) simulated +host_inst_rate 68083 # Simulator instruction rate (inst/s) +host_op_rate 87941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2866621111 # Simulator tick rate (ticks/s) +host_mem_usage 384248 # Number of bytes of host memory used +host_seconds 873.19 # Real time elapsed on the host +sim_insts 59449445 # Number of instructions simulated +sim_ops 76789092 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -20,148 +20,148 @@ system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130753040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1118144 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9587720 # Number of bytes written to this memory -system.physmem.num_reads 15117482 # Number of read requests responded to by this memory -system.physmem.num_writes 856700 # Number of write requests responded to by this memory +system.physmem.bytes_read 130740776 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1120320 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9586312 # Number of bytes written to this memory +system.physmem.num_reads 15115704 # Number of read requests responded to by this memory +system.physmem.num_writes 856678 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52232493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 446670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3830049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56062542 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119784 # number of replacements -system.l2c.tagsinuse 26074.057253 # Cycle average of tags in use -system.l2c.total_refs 1841990 # Total number of references to valid blocks. -system.l2c.sampled_refs 150687 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.223948 # Average number of references to valid blocks. +system.physmem.bw_read 52231553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 447573 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3829777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56061329 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119794 # number of replacements +system.l2c.tagsinuse 26073.611012 # Cycle average of tags in use +system.l2c.total_refs 1840774 # Total number of references to valid blocks. +system.l2c.sampled_refs 150725 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.212798 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14309.337346 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 64.598044 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.929730 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 6189.709081 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5509.483052 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11668 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 1016254 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 396465 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1577382 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 633173 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 633173 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 3357 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3357 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu.data 7 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246311 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246311 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.017089 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.048289 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985507 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu.data 246237 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246237 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 152995 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11668 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 1016254 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 642702 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1823619 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 152995 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11668 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 1016254 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 642702 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1823619 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000961 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001028 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.017104 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.048292 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.986893 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569735 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000982 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.001039 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.017089 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.248099 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000982 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.001039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.017089 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.248099 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53583.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52411.771488 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52295.753682 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 302.971188 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52587.905823 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53583.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52411.771488 # average overall miss latency _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
