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I'm not sure I understand the context. Do you want to connect the config, pio and dma port to different interconnects (bus vs ruby)? If so, why? If all the ports of the device, e.g. the ide controller, are connected to the same interconnect, then I'd suggest to rely on attachIO and just pass the Ruby sequencer in question instead of the bus. - Andreas Hansson On March 14, 2012, 8:58 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1102/ > ----------------------------------------------------------- > > (Updated March 14, 2012, 8:58 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8898:71c9357b9132 > --------------------------- > Ruby X86: problem in setting DMA port, related to changeset 8850. > I think since the dma port is assigned twice (once in SouthBridge.py, > and once by Ruby somewhere) an extra port gets created which has no > peer port. This results in a segmentation fault when a simulation is > started. The posted patch solves the problem, but it is not the > solution I am looking for. Andreas, do you have some idea how to > handle this issue? > > > Diffs > ----- > > configs/common/FSConfig.py 6df06e5975c6 > src/dev/x86/Pc.py 6df06e5975c6 > src/dev/x86/SouthBridge.py 6df06e5975c6 > > Diff: http://reviews.gem5.org/r/1102/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
