changeset 75b524b64c28 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=75b524b64c28
description:
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
diffstat:
src/arch/alpha/isa/main.isa | 2 +-
src/arch/alpha/isa_traits.hh | 2 +-
src/arch/alpha/types.hh | 2 +-
src/arch/arm/intregs.hh | 2 +-
src/arch/arm/isa/templates/neon.isa | 18 ++-
src/arch/arm/linux/atag.hh | 2 +-
src/arch/arm/miscregs.cc | 2 +-
src/arch/arm/miscregs.hh | 2 +-
src/arch/arm/nativetrace.cc | 2 +-
src/arch/arm/pagetable.hh | 2 +-
src/arch/arm/predecoder.hh | 2 +-
src/arch/arm/table_walker.hh | 2 +-
src/arch/arm/utility.hh | 2 +-
src/arch/arm/vtophys.hh | 2 +-
src/arch/x86/bios/e820.hh | 2 +-
src/arch/x86/emulenv.hh | 2 +-
src/arch/x86/faults.hh | 2 +-
src/arch/x86/isa/macroop.isa | 2 +-
src/arch/x86/isa_traits.hh | 2 +-
src/arch/x86/locked_mem.hh | 2 +-
src/arch/x86/mmapped_ipr.hh | 2 +-
src/arch/x86/nativetrace.cc | 2 +-
src/arch/x86/predecoder.hh | 2 +-
src/arch/x86/regs/float.hh | 2 +-
src/arch/x86/regs/int.hh | 2 +-
src/arch/x86/regs/misc.hh | 2 +-
src/arch/x86/regs/segment.hh | 2 +-
src/arch/x86/tlb.cc | 2 +-
src/arch/x86/types.hh | 2 +-
src/arch/x86/utility.hh | 2 +-
src/arch/x86/vtophys.hh | 2 +-
src/base/bitmap.cc | 12 +-
src/base/callback.cc | 2 +-
src/base/range.cc | 20 +-
src/base/range_map.hh | 3 +-
src/base/str.cc | 22 ++--
src/base/vnc/convert.hh | 2 +-
src/cpu/base_dyn_inst.hh | 2 +-
src/cpu/exetrace.cc | 2 +-
src/cpu/inorder/inorder_dyn_inst.hh | 2 +-
src/cpu/inorder/pipeline_traits.hh | 2 +-
src/cpu/inorder/resource.hh | 2 +-
src/cpu/inteltrace.cc | 2 +-
src/cpu/o3/dyn_inst.hh | 2 +-
src/cpu/o3/thread_context.hh | 2 +-
src/cpu/simple_thread.hh | 4 +-
src/cpu/static_inst.hh | 2 +-
src/cpu/thread_context.hh | 4 +-
src/cpu/thread_state.hh | 4 +-
src/dev/i8254xGBe.hh | 2 +-
src/dev/ide_atareg.h | 2 +-
src/dev/sinicreg.hh | 190 ++++++++++++++++++------------------
src/python/m5/params.py | 2 +-
src/sim/byteswap.hh | 8 +-
src/sim/eventq.hh | 2 +-
src/sim/serialize.hh | 15 ++-
56 files changed, 204 insertions(+), 186 deletions(-)
diffs (truncated from 986 to 300 lines):
diff -r bba76d164f9e -r 75b524b64c28 src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/alpha/isa/main.isa Mon Mar 19 06:36:09 2012 -0400
@@ -222,7 +222,7 @@
/// this class and derived classes. Maybe these should really
/// live here and not in the AlphaISA namespace.
enum DependenceTags {
- FP_Base_DepTag = AlphaISA::FP_Base_DepTag,
+ FP_Base_DepTag = AlphaISA::FP_Base_DepTag
};
/// Constructor.
diff -r bba76d164f9e -r 75b524b64c28 src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/alpha/isa_traits.hh Mon Mar 19 06:36:09 2012 -0400
@@ -119,7 +119,7 @@
MachineBytes = 8,
WordBytes = 4,
HalfwordBytes = 2,
- ByteBytes = 1,
+ ByteBytes = 1
};
// return a no-op instruction... used for instruction fetch faults
diff -r bba76d164f9e -r 75b524b64c28 src/arch/alpha/types.hh
--- a/src/arch/alpha/types.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/alpha/types.hh Mon Mar 19 06:36:09 2012 -0400
@@ -48,7 +48,7 @@
{
ANNOTE_NONE = 0,
// An impossible number for instruction annotations
- ITOUCH_ANNOTE = 0xffffffff,
+ ITOUCH_ANNOTE = 0xffffffff
};
} // namespace AlphaISA
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/intregs.hh
--- a/src/arch/arm/intregs.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/intregs.hh Mon Mar 19 06:36:09 2012 -0400
@@ -239,7 +239,7 @@
INTREG_R6_FIQ = INTREG_R6,
INTREG_R7_FIQ = INTREG_R7,
INTREG_PC_FIQ = INTREG_PC,
- INTREG_R15_FIQ = INTREG_R15,
+ INTREG_R15_FIQ = INTREG_R15
};
typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/isa/templates/neon.isa
--- a/src/arch/arm/isa/templates/neon.isa Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/isa/templates/neon.isa Mon Mar 19 06:36:09 2012 -0400
@@ -234,12 +234,16 @@
}};
output header {{
- uint16_t nextBiggerType(uint8_t);
- uint32_t nextBiggerType(uint16_t);
- uint64_t nextBiggerType(uint32_t);
- int16_t nextBiggerType(int8_t);
- int32_t nextBiggerType(int16_t);
- int64_t nextBiggerType(int32_t);
+ template <typename T>
+ struct bigger_type_t;
+
+ template<> struct bigger_type_t<uint8_t> { typedef uint16_t type; };
+ template<> struct bigger_type_t<uint16_t> { typedef uint32_t type; };
+ template<> struct bigger_type_t<uint32_t> { typedef uint64_t type; };
+
+ template<> struct bigger_type_t<int8_t> { typedef int16_t type; };
+ template<> struct bigger_type_t<int16_t> { typedef int32_t type; };
+ template<> struct bigger_type_t<int32_t> { typedef int64_t type; };
}};
def template NeonUnequalRegExecute {{
@@ -247,7 +251,7 @@
Fault %(class_name)s<Element>::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- typedef typeof(nextBiggerType((Element)0)) BigElement;
+ typedef typename bigger_type_t<Element>::type BigElement;
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/linux/atag.hh
--- a/src/arch/arm/linux/atag.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/linux/atag.hh Mon Mar 19 06:36:09 2012 -0400
@@ -51,7 +51,7 @@
RevTag = 0x54410007,
SerialTag = 0x54410006,
CmdTag = 0x54410009,
- NoneTag = 0x00000000,
+ NoneTag = 0x00000000
};
class AtagHeader
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/miscregs.cc Mon Mar 19 06:36:09 2012 -0400
@@ -499,4 +499,4 @@
return NUM_MISCREGS;
}
-};
+}
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/miscregs.hh Mon Mar 19 06:36:09 2012 -0400
@@ -529,6 +529,6 @@
Bitfield<31> l2rstDISABLE_monitor;
EndBitUnion(L2CTLR)
-};
+}
#endif // __ARCH_ARM_MISCREGS_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/nativetrace.cc
--- a/src/arch/arm/nativetrace.cc Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/nativetrace.cc Mon Mar 19 06:36:09 2012 -0400
@@ -226,4 +226,4 @@
ArmNativeTraceParams::create()
{
return new Trace::ArmNativeTrace(this);
-};
+}
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/pagetable.hh
--- a/src/arch/arm/pagetable.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/pagetable.hh Mon Mar 19 06:36:09 2012 -0400
@@ -208,6 +208,6 @@
-};
+}
#endif // __ARCH_ARM_PAGETABLE_H__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/predecoder.hh
--- a/src/arch/arm/predecoder.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/predecoder.hh Mon Mar 19 06:36:09 2012 -0400
@@ -149,6 +149,6 @@
return thisEmi;
}
};
-};
+}
#endif // __ARCH_ARM_PREDECODER_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/table_walker.hh Mon Mar 19 06:36:09 2012 -0400
@@ -325,7 +325,7 @@
/** Queue of requests that have passed are waiting because the walker is
* currently busy. */
- std::list<WalkerState *> pendingQueue;;
+ std::list<WalkerState *> pendingQueue;
/** Port to issue translation requests from */
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/utility.hh Mon Mar 19 06:36:09 2012 -0400
@@ -182,6 +182,6 @@
return tc->readMiscReg(MISCREG_CONTEXTIDR);
}
-};
+}
#endif
diff -r bba76d164f9e -r 75b524b64c28 src/arch/arm/vtophys.hh
--- a/src/arch/arm/vtophys.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/arm/vtophys.hh Mon Mar 19 06:36:09 2012 -0400
@@ -45,7 +45,7 @@
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
bool virtvalid(ThreadContext *tc, Addr vaddr);
-};
+}
#endif // __ARCH_ARM_VTOPHYS_H__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/bios/e820.hh
--- a/src/arch/x86/bios/e820.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/bios/e820.hh Mon Mar 19 06:36:09 2012 -0400
@@ -77,6 +77,6 @@
void writeTo(PortProxy& proxy, Addr countAddr, Addr addr);
};
-};
+}
#endif // __ARCH_X86_BIOS_E820_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/emulenv.hh
--- a/src/arch/x86/emulenv.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/emulenv.hh Mon Mar 19 06:36:09 2012 -0400
@@ -71,6 +71,6 @@
void doModRM(const ExtMachInst & machInst);
void setSeg(const ExtMachInst & machInst);
};
-};
+}
#endif // __ARCH_X86_TYPES_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/faults.hh Mon Mar 19 06:36:09 2012 -0400
@@ -419,6 +419,6 @@
return true;
}
};
-};
+}
#endif // __ARCH_X86_FAULTS_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/isa/macroop.isa
--- a/src/arch/x86/isa/macroop.isa Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/isa/macroop.isa Mon Mar 19 06:36:09 2012 -0400
@@ -89,7 +89,7 @@
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
- };
+ }
}};
def template MacroDisassembly {{
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/isa_traits.hh
--- a/src/arch/x86/isa_traits.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/isa_traits.hh Mon Mar 19 06:36:09 2012 -0400
@@ -85,6 +85,6 @@
SixtyFourBitMode // Behave as if we're in 64 bit
// mode (this doesn't actually matter).
};
-};
+}
#endif // __ARCH_X86_ISATRAITS_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/locked_mem.hh
--- a/src/arch/x86/locked_mem.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/locked_mem.hh Mon Mar 19 06:36:09 2012 -0400
@@ -53,6 +53,6 @@
{
return true;
}
-};
+}
#endif // __ARCH_X86_LOCKEDMEM_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/mmapped_ipr.hh
--- a/src/arch/x86/mmapped_ipr.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/mmapped_ipr.hh Mon Mar 19 06:36:09 2012 -0400
@@ -78,6 +78,6 @@
xc->setMiscReg(index, gtoh(data));
return xc->getCpuPtr()->ticks(1);
}
-};
+}
#endif // __ARCH_X86_MMAPPEDIPR_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/nativetrace.cc
--- a/src/arch/x86/nativetrace.cc Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/nativetrace.cc Mon Mar 19 06:36:09 2012 -0400
@@ -197,4 +197,4 @@
X86NativeTraceParams::create()
{
return new Trace::X86NativeTrace(this);
-};
+}
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/predecoder.hh
--- a/src/arch/x86/predecoder.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/predecoder.hh Mon Mar 19 06:36:09 2012 -0400
@@ -234,6 +234,6 @@
return emi;
}
};
-};
+}
#endif // __ARCH_X86_PREDECODER_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/regs/float.hh
--- a/src/arch/x86/regs/float.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/regs/float.hh Mon Mar 19 06:36:09 2012 -0400
@@ -150,6 +150,6 @@
{
return FLOATREG_FPR((top + index + 8) % 8);
}
-};
+}
#endif // __ARCH_X86_FLOATREGS_HH__
diff -r bba76d164f9e -r 75b524b64c28 src/arch/x86/regs/int.hh
--- a/src/arch/x86/regs/int.hh Mon Mar 19 06:35:04 2012 -0400
+++ b/src/arch/x86/regs/int.hh Mon Mar 19 06:36:09 2012 -0400
@@ -178,6 +178,6 @@
index = (index - 4) | foldBit;
return (IntRegIndex)index;
}
-};
+}
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