> On March 20, 2012, 10:47 a.m., Nilay Vaish wrote: > > Andreas, can this same functionality not implemented while retaining the > > port abstraction? I mean, why do we do we prefer using the system pointer > > for accessing physical memory? Even if the system has multiple different > > memories, can we not have a single port that has access to all those > > memories? > > > > It might be that I am asking questions asked earlier by others.
We already have that functionality in place through the actual "real" interconnect, i.e. connecting all the masters in the system to the memories, with address decoding in the interconnect. The fastmem option is just a way to avoid going through the memory system. If we make fastmem use a port then essentially we end up with a shadow interconnect next to the normal one (with address decoding etc). - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1108/#review2334 ----------------------------------------------------------- On March 20, 2012, 10:32 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1108/ > ----------------------------------------------------------- > > (Updated March 20, 2012, 10:32 a.m.) > > > Review request for Default. > > > Description > ------- > > Atomic: Remove the physmem_port and access memory directly > > This patch removes the physmem_port from the Atomic CPU and instead > uses the system pointer to access the physmem when using the fastmem > option. The system already keeps track of the physmem and the valid > memory address ranges, and with this patch we merely make use of that > existing functionality. As a result of this change, the overloaded > getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs. > > > Diffs > ----- > > configs/example/fs.py c739a3a829f5 > configs/example/se.py c739a3a829f5 > src/cpu/base.hh c739a3a829f5 > src/cpu/simple/AtomicSimpleCPU.py c739a3a829f5 > src/cpu/simple/atomic.hh c739a3a829f5 > src/cpu/simple/atomic.cc c739a3a829f5 > > Diff: http://reviews.gem5.org/r/1108/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio), > also running se.py and fs.py with --fastmem > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
