I had an assertion error caused by a page fault when running an x86 benchmark with the O3 model. The assertion is here: http://repo.gem5.org/gem5/file/c739a3a829f5/src/cpu/o3/fetch.hh#l106
When I traced back the assertion, I found that the page fault occurred while enableNX is not set. So the x86 page table walker changed the mode bits from BaseTLB::Execute to BaseTLB::Read as the following: http://repo.gem5.org/gem5/file/c739a3a829f5/src/arch/x86/pagetable_walker.cc#l703 Because the O3 fetch expects only the BaseTLB::Execute mode when a page table walk is complete, changing the mode to BaseTLB::Read triggered the assertion in the O3 fetch. It is not clear to me whether the solution is to change how the !enableNX condition is handled in the x86 page table walker or to get rid of the assertion in the O3 fetch mode. Does anyone have thoughts on this? Yasuko _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
