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src/cpu/simple/atomic.cc <http://reviews.gem5.org/r/1113/#comment2806> I wonder about caching this information vs the indirection. Since it's in the fetch paths it's going to get called a lot. src/mem/physical.cc <http://reviews.gem5.org/r/1113/#comment2807> might want to consider caching the latest start/end here to avoid the constant lookup. - Ali Saidi On March 26, 2012, 5:11 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1113/ > ----------------------------------------------------------- > > (Updated March 26, 2012, 5:11 a.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Enable multiple distributed generalized memories > > This patch removes the assumption on having on single instance of > PhysicalMemory, and enables a distributed memory where the individual > memories in the system are each responsible for a single contiguous > address range. > > All memories inherit from an AbstractMemory that encompasses the basic > behaviuor of a random access memory, and provides untimed access > methods. What was previously called PhysicalMemory is now > SimpleMemory, and a subclass of AbstractMemory. All future types of > memory controllers should inherit from AbstractMemory. > > To enable e.g. the atomic CPU and RubyPort to access the now > distributed memory, the system has a wrapper class, called > PhysicalMemory that is aware of all the memories in the system and > their associated address ranges. This class thus acts as an > infinitely-fast bus and performs address decoding for these "shortcut" > accesses. Each memory can specify that it should not be part of the > global address map (used e.g. by the functional memories by some > testers). Moreover, each memory can be configured to be reported to > the OS configuration table, useful for populating ATAG structures, and > any potential ACPI tables. > > Checkpointing support currently assumes that all memories have the > same size and organisation when creating and resuming from the > checkpoint. A future patch will enable a more flexible > re-organisation. > > > Diffs > ----- > > configs/common/FSConfig.py 50d1b7dbd23c > configs/example/memtest.py 50d1b7dbd23c > configs/example/ruby_direct_test.py 50d1b7dbd23c > configs/example/ruby_mem_test.py 50d1b7dbd23c > configs/example/ruby_network_test.py 50d1b7dbd23c > configs/example/ruby_random_test.py 50d1b7dbd23c > configs/example/se.py 50d1b7dbd23c > configs/ruby/MESI_CMP_directory.py 50d1b7dbd23c > configs/ruby/MI_example.py 50d1b7dbd23c > configs/ruby/MOESI_CMP_directory.py 50d1b7dbd23c > configs/ruby/MOESI_CMP_token.py 50d1b7dbd23c > configs/ruby/MOESI_hammer.py 50d1b7dbd23c > configs/ruby/Network_test.py 50d1b7dbd23c > configs/ruby/Ruby.py 50d1b7dbd23c > configs/splash2/cluster.py 50d1b7dbd23c > configs/splash2/run.py 50d1b7dbd23c > src/arch/alpha/remote_gdb.hh 50d1b7dbd23c > src/arch/alpha/remote_gdb.cc 50d1b7dbd23c > src/arch/arm/ArmSystem.py 50d1b7dbd23c > src/arch/arm/linux/system.cc 50d1b7dbd23c > src/arch/arm/system.cc 50d1b7dbd23c > src/arch/sparc/SparcSystem.py 50d1b7dbd23c > src/base/remote_gdb.hh 50d1b7dbd23c > src/base/remote_gdb.cc 50d1b7dbd23c > src/cpu/checker/thread_context.hh 50d1b7dbd23c > src/cpu/inorder/thread_context.hh 50d1b7dbd23c > src/cpu/o3/fetch_impl.hh 50d1b7dbd23c > src/cpu/simple/atomic.hh 50d1b7dbd23c > src/cpu/simple/atomic.cc 50d1b7dbd23c > src/dev/alpha/backdoor.cc 50d1b7dbd23c > src/dev/arm/RealView.py 50d1b7dbd23c > src/mem/AbstractMemory.py PRE-CREATION > src/mem/PhysicalMemory.py 50d1b7dbd23c > src/mem/SConscript 50d1b7dbd23c > src/mem/SimpleMemory.py PRE-CREATION > src/mem/abstract_mem.hh PRE-CREATION > src/mem/abstract_mem.cc PRE-CREATION > src/mem/physical.hh 50d1b7dbd23c > src/mem/physical.cc 50d1b7dbd23c > src/mem/ruby/system/RubyPort.cc 50d1b7dbd23c > src/mem/simple_mem.hh PRE-CREATION > src/mem/simple_mem.cc PRE-CREATION > src/sim/System.py 50d1b7dbd23c > src/sim/system.hh 50d1b7dbd23c > src/sim/system.cc 50d1b7dbd23c > tests/configs/inorder-timing.py 50d1b7dbd23c > tests/configs/memtest-ruby.py 50d1b7dbd23c > tests/configs/memtest.py 50d1b7dbd23c > tests/configs/o3-timing-checker.py 50d1b7dbd23c > tests/configs/o3-timing-mp.py 50d1b7dbd23c > tests/configs/o3-timing.py 50d1b7dbd23c > tests/configs/rubytest-ruby.py 50d1b7dbd23c > tests/configs/simple-atomic-dummychecker.py 50d1b7dbd23c > tests/configs/simple-atomic-mp.py 50d1b7dbd23c > tests/configs/simple-atomic.py 50d1b7dbd23c > tests/configs/simple-timing-mp-ruby.py 50d1b7dbd23c > tests/configs/simple-timing-mp.py 50d1b7dbd23c > tests/configs/simple-timing-ruby.py 50d1b7dbd23c > tests/configs/simple-timing.py 50d1b7dbd23c > > Diff: http://reviews.gem5.org/r/1113/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
