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Hi Andreas, Sorry it took me a couple weeks to look this patch over. It is an impressive amount of work. My biggest concern is it appears that this patch will break all existing checkpoints, correct? Your comment states that a later patch will enable checkpoint migration between different NUMA layouts, but will it also support checkpoints created prior to this change? Can you delay checking this patch in until that later patch with checkpoint support is ready to be checked in? Thanks src/sim/system.cc <http://reviews.gem5.org/r/1113/#comment2843> Does memRanges only support continous segments? Would it be possible to support physical pages striped across all NUMA memories? - Brad Beckmann On April 2, 2012, 2:34 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1113/ > ----------------------------------------------------------- > > (Updated April 2, 2012, 2:34 p.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Enable multiple distributed generalized memories > > This patch removes the assumption on having on single instance of > PhysicalMemory, and enables a distributed memory where the individual > memories in the system are each responsible for a single contiguous > address range. > > All memories inherit from an AbstractMemory that encompasses the basic > behaviuor of a random access memory, and provides untimed access > methods. What was previously called PhysicalMemory is now > SimpleMemory, and a subclass of AbstractMemory. All future types of > memory controllers should inherit from AbstractMemory. > > To enable e.g. the atomic CPU and RubyPort to access the now > distributed memory, the system has a wrapper class, called > PhysicalMemory that is aware of all the memories in the system and > their associated address ranges. This class thus acts as an > infinitely-fast bus and performs address decoding for these "shortcut" > accesses. Each memory can specify that it should not be part of the > global address map (used e.g. by the functional memories by some > testers). Moreover, each memory can be configured to be reported to > the OS configuration table, useful for populating ATAG structures, and > any potential ACPI tables. > > Checkpointing support currently assumes that all memories have the > same size and organisation when creating and resuming from the > checkpoint. A future patch will enable a more flexible > re-organisation. > > > Diffs > ----- > > configs/example/ruby_network_test.py 97f06a79b6f5 > configs/example/ruby_random_test.py 97f06a79b6f5 > configs/example/se.py 97f06a79b6f5 > configs/ruby/MESI_CMP_directory.py 97f06a79b6f5 > configs/ruby/MI_example.py 97f06a79b6f5 > configs/example/ruby_mem_test.py 97f06a79b6f5 > configs/example/ruby_direct_test.py 97f06a79b6f5 > configs/example/memtest.py 97f06a79b6f5 > configs/common/FSConfig.py 97f06a79b6f5 > configs/ruby/MOESI_CMP_directory.py 97f06a79b6f5 > configs/ruby/MOESI_CMP_token.py 97f06a79b6f5 > configs/ruby/MOESI_hammer.py 97f06a79b6f5 > configs/ruby/Network_test.py 97f06a79b6f5 > configs/ruby/Ruby.py 97f06a79b6f5 > configs/splash2/cluster.py 97f06a79b6f5 > configs/splash2/run.py 97f06a79b6f5 > src/arch/alpha/remote_gdb.hh 97f06a79b6f5 > src/arch/alpha/remote_gdb.cc 97f06a79b6f5 > src/arch/arm/ArmSystem.py 97f06a79b6f5 > src/arch/arm/linux/system.cc 97f06a79b6f5 > src/arch/arm/system.cc 97f06a79b6f5 > src/arch/sparc/SparcSystem.py 97f06a79b6f5 > src/base/remote_gdb.hh 97f06a79b6f5 > src/base/remote_gdb.cc 97f06a79b6f5 > src/cpu/checker/thread_context.hh 97f06a79b6f5 > src/cpu/inorder/thread_context.hh 97f06a79b6f5 > src/cpu/o3/fetch_impl.hh 97f06a79b6f5 > src/cpu/simple/atomic.hh 97f06a79b6f5 > src/cpu/simple/atomic.cc 97f06a79b6f5 > src/dev/alpha/backdoor.cc 97f06a79b6f5 > src/dev/arm/RealView.py 97f06a79b6f5 > src/mem/AbstractMemory.py PRE-CREATION > src/mem/PhysicalMemory.py 97f06a79b6f5 > src/mem/SConscript 97f06a79b6f5 > src/mem/SimpleMemory.py PRE-CREATION > src/mem/abstract_mem.hh PRE-CREATION > src/mem/abstract_mem.cc PRE-CREATION > src/mem/physical.hh 97f06a79b6f5 > src/mem/physical.cc 97f06a79b6f5 > src/mem/ruby/system/RubyPort.cc 97f06a79b6f5 > src/mem/simple_mem.hh PRE-CREATION > src/mem/simple_mem.cc PRE-CREATION > src/sim/System.py 97f06a79b6f5 > src/sim/system.hh 97f06a79b6f5 > src/sim/system.cc 97f06a79b6f5 > tests/configs/inorder-timing.py 97f06a79b6f5 > tests/configs/memtest-ruby.py 97f06a79b6f5 > tests/configs/memtest.py 97f06a79b6f5 > tests/configs/o3-timing-checker.py 97f06a79b6f5 > tests/configs/o3-timing-mp.py 97f06a79b6f5 > tests/configs/o3-timing.py 97f06a79b6f5 > tests/configs/rubytest-ruby.py 97f06a79b6f5 > tests/configs/simple-atomic-dummychecker.py 97f06a79b6f5 > tests/configs/simple-atomic-mp.py 97f06a79b6f5 > tests/configs/simple-atomic.py 97f06a79b6f5 > tests/configs/simple-timing-mp-ruby.py 97f06a79b6f5 > tests/configs/simple-timing-mp.py 97f06a79b6f5 > tests/configs/simple-timing-ruby.py 97f06a79b6f5 > tests/configs/simple-timing.py 97f06a79b6f5 > > Diff: http://reviews.gem5.org/r/1113/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
