changeset 7a1dfb191e3f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a1dfb191e3f
description:
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.
All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.
Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.
diffstat:
configs/common/FSConfig.py | 24 +-
configs/example/memtest.py | 4 +-
configs/example/ruby_direct_test.py | 4 +-
configs/example/ruby_mem_test.py | 4 +-
configs/example/ruby_network_test.py | 2 +-
configs/example/ruby_random_test.py | 4 +-
configs/example/se.py | 2 +-
configs/ruby/MESI_CMP_directory.py | 5 +-
configs/ruby/MI_example.py | 5 +-
configs/ruby/MOESI_CMP_directory.py | 5 +-
configs/ruby/MOESI_CMP_token.py | 5 +-
configs/ruby/MOESI_hammer.py | 5 +-
configs/ruby/Network_test.py | 5 +-
configs/ruby/Ruby.py | 7 +-
configs/splash2/cluster.py | 4 +-
configs/splash2/run.py | 2 +-
src/arch/alpha/remote_gdb.cc | 2 +-
src/arch/alpha/remote_gdb.hh | 1 -
src/arch/arm/ArmSystem.py | 4 -
src/arch/arm/linux/system.cc | 9 +-
src/arch/arm/remote_gdb.hh | 1 -
src/arch/arm/system.cc | 3 -
src/arch/mips/remote_gdb.hh | 1 -
src/arch/sparc/SparcSystem.py | 18 +-
src/arch/sparc/remote_gdb.hh | 1 -
src/base/remote_gdb.cc | 2 +-
src/base/remote_gdb.hh | 2 -
src/cpu/checker/thread_context.hh | 2 -
src/cpu/inorder/thread_context.hh | 4 -
src/cpu/o3/fetch_impl.hh | 3 +-
src/cpu/ozone/cpu.hh | 4 -
src/cpu/simple/atomic.cc | 17 +-
src/cpu/simple/atomic.hh | 2 -
src/dev/alpha/backdoor.cc | 2 +-
src/dev/arm/RealView.py | 14 +-
src/dev/ide_disk.hh | 1 -
src/mem/AbstractMemory.py | 61 ++
src/mem/PhysicalMemory.py | 41 -
src/mem/SConscript | 5 +-
src/mem/SimpleMemory.py | 49 ++
src/mem/abstract_mem.cc | 537 ++++++++++++++++++++++
src/mem/abstract_mem.hh | 250 ++++++++++
src/mem/cache/mshr.cc | 2 +-
src/mem/physical.cc | 664 ++-------------------------
src/mem/physical.hh | 236 ++-------
src/mem/ruby/system/RubyPort.cc | 6 +-
src/mem/simple_mem.cc | 167 +++++++
src/mem/simple_mem.hh | 114 ++++
src/sim/System.py | 6 +-
src/sim/system.cc | 31 +-
src/sim/system.hh | 30 +-
tests/configs/inorder-timing.py | 2 +-
tests/configs/memtest-ruby.py | 4 +-
tests/configs/memtest.py | 4 +-
tests/configs/o3-timing-checker.py | 2 +-
tests/configs/o3-timing-mp.py | 3 +-
tests/configs/o3-timing.py | 2 +-
tests/configs/rubytest-ruby.py | 2 +-
tests/configs/simple-atomic-dummychecker.py | 2 +-
tests/configs/simple-atomic-mp.py | 5 +-
tests/configs/simple-atomic.py | 2 +-
tests/configs/simple-timing-mp-ruby.py | 2 +-
tests/configs/simple-timing-mp.py | 3 +-
tests/configs/simple-timing-ruby.py | 2 +-
tests/configs/simple-timing.py | 2 +-
65 files changed, 1453 insertions(+), 963 deletions(-)
diffs (truncated from 3314 to 300 lines):
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/common/FSConfig.py Fri Apr 06 13:46:31 2012 -0400
@@ -73,7 +73,7 @@
# base address (including the PCI config space)
self.bridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
- self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.physmem.port = self.membus.master
@@ -109,7 +109,7 @@
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
- physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
self = LinuxAlphaSystem(physmem = physmem)
if not mdesc:
# generic system
@@ -178,8 +178,10 @@
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
- self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size =
'64MB'), zero = True)
- self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size
='256MB'), zero = True)
+ self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
+ zero = True)
+ self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
+ zero = True)
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.physmem.port = self.membus.master
@@ -269,8 +271,8 @@
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
- zero = True)
+ self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
+ zero = True)
else:
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
self.machine_type = machine_type
@@ -283,8 +285,10 @@
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
- self.physmem = PhysicalMemory(range =
AddrRange(self.realview.mem_start_addr,
- size = mdesc.mem()))
+ self.physmem = SimpleMemory(range =
+ AddrRange(self.realview.mem_start_addr,
+ size = mdesc.mem()),
+ conf_table_reported = True)
self.realview.setupBootLoader(self.membus, self, binary)
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
@@ -319,7 +323,7 @@
self.iobus = Bus(bus_id=0)
self.membus = MemBus(bus_id=1)
self.bridge = Bridge(delay='50ns', nack_delay='4ns')
- self.physmem = PhysicalMemory(range = AddrRange('1GB'))
+ self.physmem = SimpleMemory(range = AddrRange('1GB'))
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.physmem.port = self.membus.master
@@ -424,7 +428,7 @@
self.mem_mode = mem_mode
# Physical memory
- self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
+ self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
# Platform
self.pc = Pc()
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/example/memtest.py
--- a/configs/example/memtest.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/example/memtest.py Fri Apr 06 13:46:31 2012 -0400
@@ -140,8 +140,8 @@
prototypes.insert(0, next)
# system simulated
-system = System(funcmem = PhysicalMemory(),
- physmem = PhysicalMemory(latency = "100ns"))
+system = System(funcmem = SimpleMemory(in_addr_map = False),
+ physmem = SimpleMemory(latency = "100ns"))
def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0]
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/example/ruby_direct_test.py Fri Apr 06 13:46:31 2012 -0400
@@ -83,11 +83,11 @@
sys.exit(1)
#
-# Create the M5 system. Note that the PhysicalMemory Object isn't
+# Create the M5 system. Note that the Memory Object isn't
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(physmem = PhysicalMemory())
+system = System(physmem = SimpleMemory())
#
# Create the ruby random tester
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/example/ruby_mem_test.py Fri Apr 06 13:46:31 2012 -0400
@@ -105,8 +105,8 @@
for i in xrange(options.num_cpus) ]
system = System(cpu = cpus,
- funcmem = PhysicalMemory(),
- physmem = PhysicalMemory())
+ funcmem = SimpleMemory(in_addr_map = False),
+ physmem = SimpleMemory())
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False,
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/example/ruby_network_test.py Fri Apr 06 13:46:31 2012 -0400
@@ -103,7 +103,7 @@
# create the desired simulated system
system = System(cpu = cpus,
- physmem = PhysicalMemory())
+ physmem = SimpleMemory())
Ruby.create_system(options, system)
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/example/ruby_random_test.py Fri Apr 06 13:46:31 2012 -0400
@@ -92,11 +92,11 @@
wakeup_frequency = options.wakeup_freq)
#
-# Create the M5 system. Note that the PhysicalMemory Object isn't
+# Create the M5 system. Note that the Memory Object isn't
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(tester = tester, physmem = PhysicalMemory())
+system = System(tester = tester, physmem = SimpleMemory())
Ruby.create_system(options, system)
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/example/se.py
--- a/configs/example/se.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/example/se.py Fri Apr 06 13:46:31 2012 -0400
@@ -152,7 +152,7 @@
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
- physmem = PhysicalMemory(range=AddrRange("512MB")),
+ physmem = SimpleMemory(range=AddrRange("512MB")),
membus = Bus(), mem_mode = test_mem_mode)
# Sanity check
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/MESI_CMP_directory.py Fri Apr 06 13:46:31 2012 -0400
@@ -133,8 +133,9 @@
cntrl_count += 1
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/MI_example.py Fri Apr 06 13:46:31 2012 -0400
@@ -104,8 +104,9 @@
cntrl_count += 1
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/MOESI_CMP_directory.py Fri Apr 06 13:46:31 2012 -0400
@@ -132,8 +132,9 @@
cntrl_count += 1
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/MOESI_CMP_token.py Fri Apr 06 13:46:31 2012 -0400
@@ -155,8 +155,9 @@
cntrl_count += 1
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/MOESI_hammer.py Fri Apr 06 13:46:31 2012 -0400
@@ -130,8 +130,9 @@
cntrl_count += 1
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
#
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/Network_test.py
--- a/configs/ruby/Network_test.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/Network_test.py Fri Apr 06 13:46:31 2012 -0400
@@ -105,8 +105,9 @@
cntrl_count += 1
- phys_mem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
mem_module_size = phys_mem_size / options.num_dirs
for i in xrange(options.num_dirs):
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/ruby/Ruby.py Fri Apr 06 13:46:31 2012 -0400
@@ -172,9 +172,10 @@
total_mem_size.value += dir_cntrl.directory.size.value
dir_cntrl.directory.numa_high_bit = numa_bit
- physmem_size = long(system.physmem.range.second) - \
- long(system.physmem.range.first) + 1
- assert(total_mem_size.value == physmem_size)
+ phys_mem_size = 0
+ for mem in system.memories.unproxy(system):
+ phys_mem_size += long(mem.range.second) - long(mem.range.first) + 1
+ assert(total_mem_size.value == phys_mem_size)
ruby_profiler = RubyProfiler(ruby_system = ruby,
num_of_sequencers = len(cpu_sequencers))
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/splash2/cluster.py
--- a/configs/splash2/cluster.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/splash2/cluster.py Fri Apr 06 13:46:31 2012 -0400
@@ -211,8 +211,8 @@
# ----------------------
# Create a system, and add system wide objects
# ----------------------
-system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses, physmem =
PhysicalMemory(),
- membus = Bus(clock = busFrequency))
+system = System(cpu = all_cpus, l1_ = all_l1s, l1bus_ = all_l1buses,
+ physmem = SimpleMemory(), membus = Bus(clock = busFrequency))
system.toL2bus = Bus(clock = busFrequency)
system.l2 = L2(size = options.l2size, assoc = 8)
diff -r f51b4b4f0d5e -r 7a1dfb191e3f configs/splash2/run.py
--- a/configs/splash2/run.py Thu Apr 05 17:51:26 2012 -0400
+++ b/configs/splash2/run.py Fri Apr 06 13:46:31 2012 -0400
@@ -197,7 +197,7 @@
# ----------------------
# Create a system, and add system wide objects
# ----------------------
-system = System(cpu = cpus, physmem = PhysicalMemory(),
+system = System(cpu = cpus, physmem = SimpleMemory(),
membus = Bus(clock = busFrequency))
system.toL2bus = Bus(clock = busFrequency)
diff -r f51b4b4f0d5e -r 7a1dfb191e3f src/arch/alpha/remote_gdb.cc
--- a/src/arch/alpha/remote_gdb.cc Thu Apr 05 17:51:26 2012 -0400
+++ b/src/arch/alpha/remote_gdb.cc Fri Apr 06 13:46:31 2012 -0400
@@ -166,7 +166,7 @@
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