changeset 1b2c17565ac8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1b2c17565ac8
description:
rubytest: seperated read and write ports.
This patch allows the ruby tester to support protocols where the
i-cache and d-cache
are managed by seperate controllers.
diffstat:
configs/example/ruby_random_test.py | 10 ++-
src/cpu/testers/rubytest/Check.cc | 31 ++++++-----
src/cpu/testers/rubytest/Check.hh | 7 +-
src/cpu/testers/rubytest/CheckTable.cc | 7 +-
src/cpu/testers/rubytest/CheckTable.hh | 5 +-
src/cpu/testers/rubytest/RubyTester.cc | 86 ++++++++++++++++++++++++++-------
src/cpu/testers/rubytest/RubyTester.hh | 32 ++++++++++-
src/cpu/testers/rubytest/RubyTester.py | 4 +-
src/mem/ruby/system/Sequencer.py | 3 +
9 files changed, 134 insertions(+), 51 deletions(-)
diffs (truncated from 417 to 300 lines):
diff -r 7a1dfb191e3f -r 1b2c17565ac8 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Fri Apr 06 13:46:31 2012 -0400
+++ b/configs/example/ruby_random_test.py Fri Apr 06 13:47:06 2012 -0700
@@ -89,7 +89,8 @@
tester = RubyTester(check_flush = check_flush,
checks_to_complete = options.checks,
- wakeup_frequency = options.wakeup_freq)
+ wakeup_frequency = options.wakeup_freq,
+ num_cpus = options.num_cpus)
#
# Create the M5 system. Note that the Memory Object isn't
@@ -110,9 +111,12 @@
for ruby_port in system.ruby._cpu_ruby_ports:
#
- # Tie the ruby tester ports to the ruby cpu ports
+ # Tie the ruby tester ports to the ruby cpu read and write ports
#
- tester.cpuPort = ruby_port.slave
+ if ruby_port.support_data_reqs:
+ tester.cpuDataPort = ruby_port.slave
+ if ruby_port.support_inst_reqs:
+ tester.cpuInstPort = ruby_port.slave
#
# Tell each sequencer this is the ruby tester so that it
diff -r 7a1dfb191e3f -r 1b2c17565ac8 src/cpu/testers/rubytest/Check.cc
--- a/src/cpu/testers/rubytest/Check.cc Fri Apr 06 13:46:31 2012 -0400
+++ b/src/cpu/testers/rubytest/Check.cc Fri Apr 06 13:47:06 2012 -0700
@@ -36,8 +36,9 @@
typedef RubyTester::SenderState SenderState;
Check::Check(const Address& address, const Address& pc,
- int _num_cpu_sequencers, RubyTester* _tester)
- : m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester)
+ int _num_writers, int _num_readers, RubyTester* _tester)
+ : m_num_writers(_num_writers), m_num_readers(_num_readers),
+ m_tester_ptr(_tester)
{
m_status = TesterStatus_Idle;
@@ -80,9 +81,9 @@
{
DPRINTF(RubyTest, "initiating prefetch\n");
- int index = random() % m_num_cpu_sequencers;
+ int index = random() % m_num_readers;
RubyTester::CpuPort* port =
- safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
+ safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getReadableCpuPort(index));
Request::Flags flags;
flags.set(Request::PREFETCH);
@@ -93,8 +94,8 @@
if ((random() & 0x7) != 0) {
cmd = MemCmd::ReadReq;
- // 50% chance that the request will be an instruction fetch
- if ((random() & 0x1) == 0) {
+ // if necessary, make the request an instruction fetch
+ if (port->type == RubyTester::CpuPort::InstOnly) {
flags.set(Request::INST_FETCH);
}
} else {
@@ -135,9 +136,9 @@
DPRINTF(RubyTest, "initiating Flush\n");
- int index = random() % m_num_cpu_sequencers;
+ int index = random() % m_num_writers;
RubyTester::CpuPort* port =
- safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
+ safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getWritableCpuPort(index));
Request::Flags flags;
@@ -166,9 +167,9 @@
DPRINTF(RubyTest, "initiating Action\n");
assert(m_status == TesterStatus_Idle);
- int index = random() % m_num_cpu_sequencers;
+ int index = random() % m_num_writers;
RubyTester::CpuPort* port =
- safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
+ safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getWritableCpuPort(index));
Request::Flags flags;
@@ -231,14 +232,14 @@
DPRINTF(RubyTest, "Initiating Check\n");
assert(m_status == TesterStatus_Ready);
- int index = random() % m_num_cpu_sequencers;
+ int index = random() % m_num_readers;
RubyTester::CpuPort* port =
- safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index));
+ safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getReadableCpuPort(index));
Request::Flags flags;
- // 50% chance that the request will be an instruction fetch
- if ((random() & 0x1) == 0) {
+ // If necessary, make the request an instruction fetch
+ if (port->type == RubyTester::CpuPort::InstOnly) {
flags.set(Request::INST_FETCH);
}
@@ -363,7 +364,7 @@
{
assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready);
m_status = TesterStatus_Idle;
- m_initiatingNode = (random() % m_num_cpu_sequencers);
+ m_initiatingNode = (random() % m_num_writers);
DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode);
m_store_count = 0;
}
diff -r 7a1dfb191e3f -r 1b2c17565ac8 src/cpu/testers/rubytest/Check.hh
--- a/src/cpu/testers/rubytest/Check.hh Fri Apr 06 13:46:31 2012 -0400
+++ b/src/cpu/testers/rubytest/Check.hh Fri Apr 06 13:47:06 2012 -0700
@@ -46,8 +46,8 @@
class Check
{
public:
- Check(const Address& address, const Address& pc, int _num_cpu_sequencer,
- RubyTester* _tester);
+ Check(const Address& address, const Address& pc, int _num_writers,
+ int _num_readers, RubyTester* _tester);
void initiate(); // Does Action or Check or nether
void performCallback(NodeID proc, SubBlock* data);
@@ -74,7 +74,8 @@
Address m_address;
Address m_pc;
RubyAccessMode m_access_mode;
- int m_num_cpu_sequencers;
+ int m_num_writers;
+ int m_num_readers;
RubyTester* m_tester_ptr;
};
diff -r 7a1dfb191e3f -r 1b2c17565ac8 src/cpu/testers/rubytest/CheckTable.cc
--- a/src/cpu/testers/rubytest/CheckTable.cc Fri Apr 06 13:46:31 2012 -0400
+++ b/src/cpu/testers/rubytest/CheckTable.cc Fri Apr 06 13:47:06 2012 -0700
@@ -32,8 +32,9 @@
#include "cpu/testers/rubytest/CheckTable.hh"
#include "debug/RubyTest.hh"
-CheckTable::CheckTable(int _num_cpu_sequencers, RubyTester* _tester)
- : m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester)
+CheckTable::CheckTable(int _num_writers, int _num_readers, RubyTester* _tester)
+ : m_num_writers(_num_writers), m_num_readers(_num_readers),
+ m_tester_ptr(_tester)
{
physical_address_t physical = 0;
Address address;
@@ -94,7 +95,7 @@
}
Check* check_ptr = new Check(address, Address(100 + m_check_vector.size()),
- m_num_cpu_sequencers, m_tester_ptr);
+ m_num_writers, m_num_readers, m_tester_ptr);
for (int i = 0; i < CHECK_SIZE; i++) {
// Insert it once per byte
m_lookup_map[Address(address.getAddress() + i)] = check_ptr;
diff -r 7a1dfb191e3f -r 1b2c17565ac8 src/cpu/testers/rubytest/CheckTable.hh
--- a/src/cpu/testers/rubytest/CheckTable.hh Fri Apr 06 13:46:31 2012 -0400
+++ b/src/cpu/testers/rubytest/CheckTable.hh Fri Apr 06 13:47:06 2012 -0700
@@ -43,7 +43,7 @@
class CheckTable
{
public:
- CheckTable(int _num_cpu_sequencers, RubyTester* _tester);
+ CheckTable(int _num_writers, int _num_readers, RubyTester* _tester);
~CheckTable();
Check* getRandomCheck();
@@ -66,7 +66,8 @@
std::vector<Check*> m_check_vector;
m5::hash_map<Address, Check*> m_lookup_map;
- int m_num_cpu_sequencers;
+ int m_num_writers;
+ int m_num_readers;
RubyTester* m_tester_ptr;
};
diff -r 7a1dfb191e3f -r 1b2c17565ac8 src/cpu/testers/rubytest/RubyTester.cc
--- a/src/cpu/testers/rubytest/RubyTester.cc Fri Apr 06 13:46:31 2012 -0400
+++ b/src/cpu/testers/rubytest/RubyTester.cc Fri Apr 06 13:47:06 2012 -0700
@@ -53,17 +53,37 @@
RubyTester::RubyTester(const Params *p)
: MemObject(p), checkStartEvent(this),
_masterId(p->system->getMasterId(name())),
+ m_num_cpus(p->num_cpus),
m_checks_to_complete(p->checks_to_complete),
m_deadlock_threshold(p->deadlock_threshold),
m_wakeup_frequency(p->wakeup_frequency),
- m_check_flush(p->check_flush)
+ m_check_flush(p->check_flush),
+ m_num_inst_ports(p->port_cpuInstPort_connection_count)
{
m_checks_completed = 0;
- // create the ports
- for (int i = 0; i < p->port_cpuPort_connection_count; ++i) {
- ports.push_back(new CpuPort(csprintf("%s-port%d", name(), i),
- this, i));
+ //
+ // Create the requested inst and data ports and place them on the
+ // appropriate read and write port lists. The reason for the subtle
+ // difference between inst and data ports vs. read and write ports is
+ // from the tester's perspective, it only needs to know whether a port
+ // supports reads (checks) or writes (actions). Meanwhile, the protocol
+ // controllers have data ports (support read and writes) or inst ports
+ // (support only reads).
+ // Note: the inst ports are the lowest elements of the readPort vector,
+ // then the data ports are added to the readPort vector
+ //
+ for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) {
+ readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i),
+ this, i,
+ RubyTester::CpuPort::InstOnly));
+ }
+ for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) {
+ CpuPort *port = NULL;
+ port = new CpuPort(csprintf("%s-dataPort%d", name(), i), this, i,
+ RubyTester::CpuPort::DataOnly);
+ readPorts.push_back(port);
+ writePorts.push_back(port);
}
// add the check start event to the event queue
@@ -73,37 +93,57 @@
RubyTester::~RubyTester()
{
delete m_checkTable_ptr;
- for (int i = 0; i < ports.size(); i++)
- delete ports[i];
+ // Only delete the readPorts since the writePorts are just a subset
+ for (int i = 0; i < readPorts.size(); i++)
+ delete readPorts[i];
}
void
RubyTester::init()
{
- assert(ports.size() > 0);
+ assert(writePorts.size() > 0 && readPorts.size() > 0);
- m_last_progress_vector.resize(ports.size());
+ m_last_progress_vector.resize(m_num_cpus);
for (int i = 0; i < m_last_progress_vector.size(); i++) {
m_last_progress_vector[i] = 0;
}
- m_num_cpu_sequencers = ports.size();
+ m_num_writers = writePorts.size();
+ m_num_readers = readPorts.size();
- m_checkTable_ptr = new CheckTable(m_num_cpu_sequencers, this);
+ m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
}
MasterPort &
RubyTester::getMasterPort(const std::string &if_name, int idx)
{
- if (if_name != "cpuPort") {
+ if (if_name != "cpuInstPort" && if_name != "cpuDataPort") {
// pass it along to our super class
return MemObject::getMasterPort(if_name, idx);
} else {
- if (idx >= static_cast<int>(ports.size())) {
- panic("RubyTester::getMasterPort: unknown index %d\n", idx);
+ if (if_name == "cpuInstPort") {
+ printf("print getting inst port %d\n", idx);
+ if (idx > m_num_inst_ports) {
+ panic("RubyTester::getMasterPort: unknown inst port idx %d\n",
+ idx);
+ }
+ //
+ // inst ports directly map to the lowest readPort elements
+ //
+ return *readPorts[idx];
+ } else {
+ assert(if_name == "cpuDataPort");
+ //
+ // add the inst port offset to translate to the correct read port
+ // index
+ //
+ int read_idx = idx + m_num_inst_ports;
+ if (read_idx >= static_cast<int>(readPorts.size())) {
+ panic("RubyTester::getMasterPort: unknown data port idx %d\n",
+ idx);
+ }
+ return *readPorts[read_idx];
}
-
- return *ports[idx];
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