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I don't think we should check this in since it creates microops which only partially mitigate the problem and don't solve it. They would have to be used in all the macroops where they made sense, and I doubt there are any naturally occurring instances of microops which really write *all* the flags. When it is solved, then they'll be useless and need to be cleaned up. It's reasonable, though, for this change to stay up here for people to grab if they have an urgent need for this specific functionality in the short term, like the person who needed to loop tightly over a few add instructions. - Gabe Black On April 12, 2012, 5:38 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1148/ > ----------------------------------------------------------- > > (Updated April 12, 2012, 5:38 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8945:31d20d9ac126 > --------------------------- > x86: Different microop if all flag bits are written > This patch changes the isa files, so that a new microop is generated > for a instruction if it rights all flags. This will help in case of > the o3 cpu, as this new microop does not read the flags register. > > > Diffs > ----- > > src/arch/x86/isa/microops/regop.isa d062cc7a8bdf > > Diff: http://reviews.gem5.org/r/1148/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
