> On April 12, 2012, 6:09 p.m., Gabe Black wrote: > > I don't think we should check this in since it creates microops which only > > partially mitigate the problem and don't solve it. They would have to be > > used in all the macroops where they made sense, and I doubt there are any > > naturally occurring instances of microops which really write *all* the > > flags. When it is solved, then they'll be useless and need to be cleaned up. > > > > It's reasonable, though, for this change to stay up here for people to grab > > if they have an urgent need for this specific functionality in the short > > term, like the person who needed to loop tightly over a few add > > instructions. > > Nilay Vaish wrote: > This part of the complete solution. Even in the complete solution we will > need to > check that if a microop is going to write all the bits of, say the ZAPS > register, > then we should not be reading that register. > > Gabe Black wrote: > No it is not. We are *not* going to implement a whole new version of each > microop to write to every combination of flag bits or groups of flag bits. As > previously stated (repeatedly) that will result in lots and lots of different > flavors of microops, and that's as unacceptable as it is unnecessary.
I think I see what you were going for here. You don't literally mean *all* the flags, you mean all the flags involved. So if you're writing ZAPS, you're writing it all and don't need to read it first. That makes more sense, but I still don't think it's a direction we should go. There will only be one group of flags which could be partially updated, and all the existing macroops would have to be updated to use the new microops where necessary. Changes here either need to solve the problem more completely or induce less complexity and change less existing code. - Gabe ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1148/#review2537 ----------------------------------------------------------- On April 12, 2012, 5:38 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1148/ > ----------------------------------------------------------- > > (Updated April 12, 2012, 5:38 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8945:31d20d9ac126 > --------------------------- > x86: Different microop if all flag bits are written > This patch changes the isa files, so that a new microop is generated > for a instruction if it rights all flags. This will help in case of > the o3 cpu, as this new microop does not read the flags register. > > > Diffs > ----- > > src/arch/x86/isa/microops/regop.isa d062cc7a8bdf > > Diff: http://reviews.gem5.org/r/1148/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
