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I don't understand what this patch is doing. It looks like you're adding members to keep track of flag bits and that sort of thing. If we didn't keep track of that before, we probably don't need to keep track of it now. Could you please explain what you're implementing here? src/arch/x86/insts/microop.hh <http://reviews.gem5.org/r/1160/#comment2969> What are these functions for? - Gabe Black On April 21, 2012, 1:20 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1160/ > ----------------------------------------------------------- > > (Updated April 21, 2012, 1:20 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8962:1c063dca6858 > --------------------------- > X86: Runtime read, write conditions for CCFlagBits register > This patch introduces runtime read, write conditions for CCFlagBits register. > The main idea is that each microop, while being used in the microcode, > should specify the condition code flags it would read and write. On the > basis of this info, at runtime, it would be decided which condition code > registers should be read and written. This would help in reducing the extent > of RAW dependence while using the o3 cpu with x86. Currently, the flags that > would read and written are specified together. Next couple of patches would > try to look in to splitting the flags in to read and write sets and split the > ccFlagBits register. > > > Diffs > ----- > > src/arch/x86/insts/micromediaop.hh 0bba1c59b4d1 > src/arch/x86/insts/microop.hh 0bba1c59b4d1 > src/arch/x86/insts/microregop.hh 0bba1c59b4d1 > src/arch/x86/isa/microops/debug.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/mediaop.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/regop.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/seqop.isa 0bba1c59b4d1 > src/arch/x86/isa/microops/specop.isa 0bba1c59b4d1 > src/arch/x86/isa/operands.isa 0bba1c59b4d1 > > Diff: http://reviews.gem5.org/r/1160/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
