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Ship it! Looks good. The only thing I'd change is to remove the space between the two groups of shuffle microops to be consistent with the register only one and to not reuse ufp1 and ufp2. There micro floating point registers go up to ufp7, and by spreading it out we'll make things easier for a dumber pipeline that isn't good at resolving register dependencies. I'll make those two changes and get this in the repository. Thanks! - Gabe Black On May 15, 2012, 5:43 p.m., Marc Orr wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1189/ > ----------------------------------------------------------- > > (Updated May 15, 2012, 5:43 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8981:7742f432fc1d > --------------------------- > x86 ISA: Implement the sse3 haddps instruction. > > This patch is a revised version of Vince Weaver's patch from 592. > > > Diffs > ----- > > src/arch/x86/isa/decoder/two_byte_opcodes.isa > 4388495beb44ba859d20177371caf9e14902ef91 > > src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py > 4388495beb44ba859d20177371caf9e14902ef91 > > Diff: http://reviews.gem5.org/r/1189/diff/ > > > Testing > ------- > > Wrote a little program that uses haddps. All 3 haddps versions were tested > (XMM_XMM, XMM_M, and XMM_P). > > > Thanks, > > Marc Orr > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
