----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1092/#review2694 -----------------------------------------------------------
I've recently tried using this patch to get switchout functionality working, as others on the mailing list have pointed out there are still many assertions failures as well as failures related to the specific ISA being used. src/cpu/o3/commit_impl.hh <http://reviews.gem5.org/r/1092/#comment3046> == true is unnecessary and makes code less readable. src/cpu/o3/fetch_impl.hh <http://reviews.gem5.org/r/1092/#comment3047> I know NULL is used extensively in gem5 but, should we prefer 0? - Anthony Gutierrez On March 16, 2012, 7:40 a.m., Andrew Lukefahr wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1092/ > ----------------------------------------------------------- > > (Updated March 16, 2012, 7:40 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8896:6f0169698281 > --------------------------- > fixed drainCount > > > Diffs > ----- > > src/cpu/base.cc ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/cpu/o3/commit_impl.hh ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/cpu/o3/cpu.cc ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/cpu/o3/fetch_impl.hh ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/cpu/o3/iew.hh ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/cpu/o3/lsq_unit.hh ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/sim/eventq.cc ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/sim/sim_events.hh ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/sim/sim_events.cc ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/sim/sim_exit.hh ad5f1f128fafebd4c6641f72c7872d669c1dc239 > src/sim/simulate.cc ad5f1f128fafebd4c6641f72c7872d669c1dc239 > > Diff: http://reviews.gem5.org/r/1092/diff/ > > > Testing > ------- > > Allows multiple switchouts of O3CPU using the attached config file. > > Both CPU's maintain separate (overlapping) seqNums, see > ./src/cpu/o3/cpu.cc:1239 for further detail... > > > Thanks, > > Andrew Lukefahr > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
