Hi, I'm interested in using an in order ARM model. Based on the documentation I've found and my search through the lists and Mercurial, it seems that this is not supported. I've seen some traffic on this topic in the past couple months, and was wondering if anyone had (even a half working) patch for this to get started with or could point me to a good place to start.
Our higher level goal is to explore some cache optimizations on in order cores. Our code is generated using LLVM and cross compiled to a gem5 target. Since, LLVM does not support Alpha well, we would like to use ARM (preferred) or MIPS. We did try using MIPS as well, but the code generated by the cs cross compiler fails with std::bad_alloc during a call to writev in system_emul.hh because it tries to allocate an array of length 0. The sample binary does run to completion. I would appreciate help in moving us forward with either patching an in order model for ARM or getting MIPS to run binaries generated by cs cross compiler. Thanks, Tarun _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
