On Thu, 24 May 2012, Gabe Black wrote:
Some quick testing shows that splitting the x86 condition code register up adds about an 8% penalty on twolf simple atomic, relative to a version of gem5 with some performance improvements that aren't checked in yet. That's ok since this is something that needs to happen, but that shows the overhead of reading the extra registers. Avoiding reading any unnecessary registers (including the zero register as a placeholder/substitute) will help recover that lost performance.
Gabe, what performance improvements do you have in mind? We had discussed before the possibility of the registers read/written by a microop being decided at the time of construction of the microop, instead of at compile time. From the discussion it seemed that we would need to assess the execution time impact of such any such change as it would probably affect all the ISAs.
-- Nilay _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
