> On May 31, 2012, 2:53 p.m., Nilay Vaish wrote: > > src/cpu/o3/dyn_inst.hh, line 111 > > <http://reviews.gem5.org/r/1241/diff/1/?file=27179#file27179line111> > > > > Should we hard code this value of 3? > > Ali Saidi wrote: > I'm fine with it. It was experimentally determined and an assert will > catch it.
will change the isa parser - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1241/#review2871 ----------------------------------------------------------- On May 30, 2012, 3:13 p.m., Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1241/ > ----------------------------------------------------------- > > (Updated May 30, 2012, 3:13 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9037:350f47d32f56 > --------------------------- > O3: Clean up the O3 structures and try to pack them a bit better. > > DynInst is extremely large the hope is that this re-organization will put the > most used members close to each other. > > > Diffs > ----- > > src/cpu/base_dyn_inst.hh 8b9f227b64d8 > src/cpu/base_dyn_inst_impl.hh 8b9f227b64d8 > src/cpu/o3/bpred_unit.hh 8b9f227b64d8 > src/cpu/o3/comm.hh 8b9f227b64d8 > src/cpu/o3/commit_impl.hh 8b9f227b64d8 > src/cpu/o3/decode_impl.hh 8b9f227b64d8 > src/cpu/o3/dyn_inst.hh 8b9f227b64d8 > src/cpu/o3/dyn_inst_impl.hh 8b9f227b64d8 > src/cpu/o3/iew_impl.hh 8b9f227b64d8 > src/cpu/o3/inst_queue_impl.hh 8b9f227b64d8 > src/cpu/o3/lsq_unit.hh 8b9f227b64d8 > src/cpu/o3/lsq_unit_impl.hh 8b9f227b64d8 > src/cpu/o3/rename_impl.hh 8b9f227b64d8 > > Diff: http://reviews.gem5.org/r/1241/diff/ > > > Testing > ------- > > > Thanks, > > Ali Saidi > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
