Hi everyone, In preparation for the introduction of the long-awaited SimpleDRAM model, I am making the SimpleMemory a single-ported memory controller, i.e. replacing the VectorSlavePort with a SlavePort. For most regressions this is not a problem as we rely on the bus to do any (de)multiplexing. However, for some of the synthetic test cases, the change causes issues, and most notably so for the memtester (and some Ruby testers).
My question is: why do we need the funcmem is the memtester? Can we not simply rely on the one-single memory and the timing vs functional accesses to this memory? If we really need a second memory then I propose to introduce a "funcbus" that does the (de)multiplexing between the testers and the funcmem. Sounds reasonable? Thanks, Andreas -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
