On Tue, 12 Jun 2012, Andreas Hansson wrote:
Hi everyone,
In preparation for the introduction of the long-awaited SimpleDRAM
model, I am making the SimpleMemory a single-ported memory controller,
i.e. replacing the VectorSlavePort with a SlavePort. For most
regressions this is not a problem as we rely on the bus to do any
(de)multiplexing. However, for some of the synthetic test cases, the
change causes issues, and most notably so for the memtester (and some
Ruby testers).
My question is: why do we need the funcmem is the memtester? Can we not
simply rely on the one-single memory and the timing vs functional
accesses to this memory?
Seems fine to me, but I think memtest should still be able to test a
system with multiple memories. It might be that two were kept separate to
avoid mixing of requests.
If we really need a second memory then I propose to introduce a
"funcbus" that does the (de)multiplexing between the testers and the
funcmem.
Sounds reasonable?
Seems in line with what I am thinking.
--
Nilay
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