changeset 6521b0f1db5b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=6521b0f1db5b
description:
test: Restore eio ref files clobbered in rev 8800b05e1cb3.
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
diffstat:
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr | 15 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout | 11 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt | 80 +
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr | 15 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout | 11 +-
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt | 330 ++
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr | 19 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout | 17 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt | 749
++++++
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr | 19 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout | 17 +-
tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt | 1181
++++++++++
12 files changed, 2416 insertions(+), 48 deletions(-)
diffs (truncated from 2528 to 300 lines):
diff -r 65423863d963 -r 6521b0f1db5b
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr Sun Jul
22 20:31:24 2012 -0500
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr Mon Jul
23 00:33:05 2012 -0400
@@ -1,9 +1,6 @@
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
diff -r 65423863d963 -r 6521b0f1db5b
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout Sun Jul
22 20:31:24 2012 -0500
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout Mon Jul
23 00:33:05 2012 -0400
@@ -1,7 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:37:08
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re
tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 250015500 because a thread reached the max instruction count
diff -r 65423863d963 -r 6521b0f1db5b
tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Sun Jul
22 20:31:24 2012 -0500
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Mon Jul
23 00:33:05 2012 -0400
@@ -0,0 +1,80 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000250 #
Number of seconds simulated
+sim_ticks 250015500 #
Number of ticks simulated
+final_tick 250015500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_freq 1000000000000 #
Frequency of simulated ticks
+host_inst_rate 3174528 #
Simulator instruction rate (inst/s)
+host_op_rate 3174125 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1586983445 #
Simulator tick rate (ticks/s)
+host_mem_usage 203780 #
Number of bytes of host memory used
+host_seconds 0.16 #
Real time elapsed on the host
+sim_insts 500001 #
Number of instructions simulated
+sim_ops 500001 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read 2872676 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read 2000076 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written 417562 #
Number of bytes written to this memory
+system.physmem.num_reads 624454 #
Number of read requests responded to by this memory
+system.physmem.num_writes 56340 #
Number of write requests responded to by this memory
+system.physmem.num_other 0 #
Number of other requests responded to by this memory
+system.physmem.bw_read 11489991621 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 7999808012 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1670144451 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 13160136072 #
Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.read_hits 124435 #
DTB read hits
+system.cpu.dtb.read_misses 8 #
DTB read misses
+system.cpu.dtb.read_acv 0 #
DTB read access violations
+system.cpu.dtb.read_accesses 124443 #
DTB read accesses
+system.cpu.dtb.write_hits 56340 #
DTB write hits
+system.cpu.dtb.write_misses 10 #
DTB write misses
+system.cpu.dtb.write_acv 0 #
DTB write access violations
+system.cpu.dtb.write_accesses 56350 #
DTB write accesses
+system.cpu.dtb.data_hits 180775 #
DTB hits
+system.cpu.dtb.data_misses 18 #
DTB misses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_accesses 180793 #
DTB accesses
+system.cpu.itb.fetch_hits 500019 #
ITB hits
+system.cpu.itb.fetch_misses 13 #
ITB misses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_accesses 500032 #
ITB accesses
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.workload.num_syscalls 18 #
Number of system calls
+system.cpu.numCycles 500032 #
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
+system.cpu.committedInsts 500001 #
Number of instructions committed
+system.cpu.committedOps 500001 #
Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 474689 #
Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 32 #
Number of float alu accesses
+system.cpu.num_func_calls 14357 #
number of times a function call or return occured
+system.cpu.num_conditional_control_insts 38180 #
number of instructions that are conditional controls
+system.cpu.num_int_insts 474689 #
number of integer instructions
+system.cpu.num_fp_insts 32 #
number of float instructions
+system.cpu.num_int_register_reads 654286 #
number of times the integer registers were read
+system.cpu.num_int_register_writes 371542 #
number of times the integer registers were written
+system.cpu.num_fp_register_reads 32 #
number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 #
number of times the floating registers were written
+system.cpu.num_mem_refs 180793 #
number of memory refs
+system.cpu.num_load_insts 124443 #
Number of load instructions
+system.cpu.num_store_insts 56350 #
Number of store instructions
+system.cpu.num_idle_cycles 0 #
Number of idle cycles
+system.cpu.num_busy_cycles 500032 #
Number of busy cycles
+system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+system.cpu.idle_fraction 0 #
Percentage of idle cycles
+
+---------- End Simulation Statistics ----------
diff -r 65423863d963 -r 6521b0f1db5b
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr Sun Jul
22 20:31:24 2012 -0500
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr Mon Jul
23 00:33:05 2012 -0400
@@ -1,9 +1,6 @@
-Traceback (most recent call last):
- File "<string>", line 1, in <module>
- File "/n/piton/z/nate/work/m5/work/src/python/m5/main.py", line 357, in main
- exec filecode in scope
- File "tests/run.py", line 78, in <module>
- execfile(joinpath(tests_root, category, mode, name, 'test.py'))
- File "tests/quick/se/20.eio-short/test.py", line 29, in <module>
- root.system.cpu.workload = EioProcess(file = binpath('anagram',
-NameError: name 'EioProcess' is not defined
+warn: Sockets disabled, not accepting gdb connections
+warn: Prefetch instructions in Alpha do not do anything
+warn: Prefetch instructions in Alpha do not do anything
+hack: be nice to actually delete the event here
+
+gzip: stdout: Broken pipe
diff -r 65423863d963 -r 6521b0f1db5b
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout Sun Jul
22 20:31:24 2012 -0500
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout Mon Jul
23 00:33:05 2012 -0400
@@ -1,7 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:36:31
-gem5 started May 8 2012 15:37:07
-gem5 executing on piton
+gem5 compiled Feb 29 2012 00:47:21
+gem5 started Feb 29 2012 00:51:57
+gem5 executing on zizzer
command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re
tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+main dictionary has 1245 entries
+49508 bytes wasted
+>Exiting @ tick 727929000 because a thread reached the max instruction count
diff -r 65423863d963 -r 6521b0f1db5b
tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt Sun Jul
22 20:31:24 2012 -0500
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt Mon Jul
23 00:33:05 2012 -0400
@@ -0,0 +1,330 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000728 #
Number of seconds simulated
+sim_ticks 727929000 #
Number of ticks simulated
+final_tick 727929000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_freq 1000000000000 #
Frequency of simulated ticks
+host_inst_rate 1742138 #
Simulator instruction rate (inst/s)
+host_op_rate 1742023 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2535976572 #
Simulator tick rate (ticks/s)
+host_mem_usage 212652 #
Number of bytes of host memory used
+host_seconds 0.29 #
Real time elapsed on the host
+sim_insts 500001 #
Number of instructions simulated
+sim_ops 500001 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read 54848 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read 25792 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written 0 #
Number of bytes written to this memory
+system.physmem.num_reads 857 #
Number of read requests responded to by this memory
+system.physmem.num_writes 0 #
Number of write requests responded to by this memory
+system.physmem.num_other 0 #
Number of other requests responded to by this memory
+system.physmem.bw_read 75348008 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 35432027 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total 75348008 #
Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.fetch_hits 0 #
ITB hits
+system.cpu.dtb.fetch_misses 0 #
ITB misses
+system.cpu.dtb.fetch_acv 0 #
ITB acv
+system.cpu.dtb.fetch_accesses 0 #
ITB accesses
+system.cpu.dtb.read_hits 124435 #
DTB read hits
+system.cpu.dtb.read_misses 8 #
DTB read misses
+system.cpu.dtb.read_acv 0 #
DTB read access violations
+system.cpu.dtb.read_accesses 124443 #
DTB read accesses
+system.cpu.dtb.write_hits 56340 #
DTB write hits
+system.cpu.dtb.write_misses 10 #
DTB write misses
+system.cpu.dtb.write_acv 0 #
DTB write access violations
+system.cpu.dtb.write_accesses 56350 #
DTB write accesses
+system.cpu.dtb.data_hits 180775 #
DTB hits
+system.cpu.dtb.data_misses 18 #
DTB misses
+system.cpu.dtb.data_acv 0 #
DTB access violations
+system.cpu.dtb.data_accesses 180793 #
DTB accesses
+system.cpu.itb.fetch_hits 500020 #
ITB hits
+system.cpu.itb.fetch_misses 13 #
ITB misses
+system.cpu.itb.fetch_acv 0 #
ITB acv
+system.cpu.itb.fetch_accesses 500033 #
ITB accesses
+system.cpu.itb.read_hits 0 #
DTB read hits
+system.cpu.itb.read_misses 0 #
DTB read misses
+system.cpu.itb.read_acv 0 #
DTB read access violations
+system.cpu.itb.read_accesses 0 #
DTB read accesses
+system.cpu.itb.write_hits 0 #
DTB write hits
+system.cpu.itb.write_misses 0 #
DTB write misses
+system.cpu.itb.write_acv 0 #
DTB write access violations
+system.cpu.itb.write_accesses 0 #
DTB write accesses
+system.cpu.itb.data_hits 0 #
DTB hits
+system.cpu.itb.data_misses 0 #
DTB misses
+system.cpu.itb.data_acv 0 #
DTB access violations
+system.cpu.itb.data_accesses 0 #
DTB accesses
+system.cpu.workload.num_syscalls 18 #
Number of system calls
+system.cpu.numCycles 1455858 #
number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 #
number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 #
number of work items this cpu completed
+system.cpu.committedInsts 500001 #
Number of instructions committed
+system.cpu.committedOps 500001 #
Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 474689 #
Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 32 #
Number of float alu accesses
+system.cpu.num_func_calls 14357 #
number of times a function call or return occured
+system.cpu.num_conditional_control_insts 38180 #
number of instructions that are conditional controls
+system.cpu.num_int_insts 474689 #
number of integer instructions
+system.cpu.num_fp_insts 32 #
number of float instructions
+system.cpu.num_int_register_reads 654286 #
number of times the integer registers were read
+system.cpu.num_int_register_writes 371542 #
number of times the integer registers were written
+system.cpu.num_fp_register_reads 32 #
number of times the floating registers were read
+system.cpu.num_fp_register_writes 16 #
number of times the floating registers were written
+system.cpu.num_mem_refs 180793 #
number of memory refs
+system.cpu.num_load_insts 124443 #
Number of load instructions
+system.cpu.num_store_insts 56350 #
Number of store instructions
+system.cpu.num_idle_cycles 0 #
Number of idle cycles
+system.cpu.num_busy_cycles 1455858 #
Number of busy cycles
+system.cpu.not_idle_fraction 1 #
Percentage of non-idle cycles
+system.cpu.idle_fraction 0 #
Percentage of idle cycles
+system.cpu.icache.replacements 0 #
number of replacements
+system.cpu.icache.tagsinuse 264.952126 #
Cycle average of tags in use
+system.cpu.icache.total_refs 499617 #
Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 403 #
Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 1239.744417 #
Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 264.952126 #
Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.129371 #
Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.129371 #
Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 499617 #
number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 499617 #
number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 499617 #
number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 499617 #
number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 499617 #
number of overall hits
+system.cpu.icache.overall_hits::total 499617 #
number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 403
# number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 403 #
number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 403 #
number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 403 #
number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 403
# number of overall misses
+system.cpu.icache.overall_misses::total 403 #
number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 22568000
# number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 22568000
# number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 22568000
# number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 22568000
# number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 22568000
# number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 22568000
# number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 500020
# number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 500020 #
number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 500020
# number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 500020 #
number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 500020
# number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 500020 #
number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000806
# miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000806
# miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000806
# miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000
# average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000
# average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000
# average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 0
# number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0
# number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 0 #
number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 #
number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
# average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
+system.cpu.icache.fast_writes 0 #
number of fast writes performed
+system.cpu.icache.cache_copies 0 #
number of cache copies performed
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403
# number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 403
# number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 403
# number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 403
# number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 403
# number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 403
# number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21359000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 21359000
# number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21359000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 21359000
# number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21359000
# number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 21359000
# number of overall MSHR miss cycles
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