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Ship it! Ship It! - Ali Saidi On July 28, 2012, 10:12 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1315/ > ----------------------------------------------------------- > > (Updated July 28, 2012, 10:12 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9145:85d0fc326753 > --------------------------- > Packet: Remove NACKs from packet and its use in endpoints > > This patch removes the NACK frrom the packet as there is no longer any > module in the system that issues them (the bridge was the only one and > the previous patch removes that). > > The handling of NACKs was mostly avoided throughout the code base, by > using e.g. panic or assert false, but in a few locations the NACKs > were actually dealt with (although NACKs never occured in any of the > regressions). Most notably, the DMA port will now never receive a NACK > and the backoff time is thus never changed. As a consequence, the > entire backoff mechanism (similar to a PCI bus) is now removed and the > DMA port entirely relies on the bus performing the arbitration and > issuing a retry when appropriate. This is more in line with e.g. PCIe. > > Surprisingly, this patch has no impact on any of the regressions. As > mentioned in the patch that removes the NACK from the bridge, a > follow-up patch should change the request and response buffer size for > at least one regression to also verify that the system behaves as > expected when the bridge fills up. > > > Diffs > ----- > > src/arch/arm/ArmTLB.py 64d4c9d8a384 > src/arch/arm/table_walker.hh 64d4c9d8a384 > src/arch/arm/table_walker.cc 64d4c9d8a384 > src/arch/x86/pagetable_walker.cc 64d4c9d8a384 > src/cpu/o3/fetch_impl.hh 64d4c9d8a384 > src/cpu/o3/lsq_unit_impl.hh 64d4c9d8a384 > src/cpu/simple/timing.cc 64d4c9d8a384 > src/dev/Device.py 64d4c9d8a384 > src/dev/copy_engine.cc 64d4c9d8a384 > src/dev/dma_device.hh 64d4c9d8a384 > src/dev/dma_device.cc 64d4c9d8a384 > src/mem/cache/cache_impl.hh 64d4c9d8a384 > src/mem/packet.hh 64d4c9d8a384 > src/mem/packet.cc 64d4c9d8a384 > > Diff: http://reviews.gem5.org/r/1315/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
