> On Aug. 7, 2012, 11:57 a.m., Nathan Binkert wrote: > > I'm honestly not a big fan of CycleCount. I'd much rather see Cycle. Is > > there something already called Cycle that would clash? I know it's not as > > descriptive, but it's used all over the place and shouldn't take long to > > get used to. Tick isn't TickCount.
The reason Tick isn't TickCount is Tick is absolute, while CycleCount is supposed to only be relative. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1338/#review3228 ----------------------------------------------------------- On Aug. 3, 2012, 5:58 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1338/ > ----------------------------------------------------------- > > (Updated Aug. 3, 2012, 5:58 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9144:2056fa4fe069 > --------------------------- > Clock: Add a CycleCount wrapper class and use where applicable > > This patch addresses the comments and feedback on the preceding patch > that reworks the clocks and now more clearly shows where cycles (or > rather cycle counts) are used to express time. > > Instead of bumping the existing patch I chose to make this a separate > patch, merely to try and focus the discussion around a smaller set of > changes. The two patches will be pushed together though. > > This changes done as part of this patch are mostly following directly > from the introduction of the wrapper class, and change enough code to > make things compile and run again. There are definitely more places > where int/uint/Tick is still used to represent cycles, and it will > take some time to chase them all down. Similarly, a lot of parameters > should be changed from Param.Tick and Param.Unsigned to > Param.CycleCount. > > An additional change that would be appropriate in the future is to > perform a similar wrapping of Tick and probably also introduce a > TickCount along with suitable operators for all these classes. > > > Diffs > ----- > > src/arch/alpha/mmapped_ipr.hh b4d0bdb52694 > src/arch/alpha/utility.hh b4d0bdb52694 > src/arch/arm/mmapped_ipr.hh b4d0bdb52694 > src/arch/arm/table_walker.cc b4d0bdb52694 > src/arch/arm/utility.hh b4d0bdb52694 > src/arch/mips/isa.hh b4d0bdb52694 > src/arch/mips/isa.cc b4d0bdb52694 > src/arch/mips/mmapped_ipr.hh b4d0bdb52694 > src/arch/mips/mt.hh b4d0bdb52694 > src/arch/mips/utility.cc b4d0bdb52694 > src/arch/power/mmapped_ipr.hh b4d0bdb52694 > src/arch/power/utility.hh b4d0bdb52694 > src/arch/sparc/mmapped_ipr.hh b4d0bdb52694 > src/arch/sparc/tlb.hh b4d0bdb52694 > src/arch/sparc/tlb.cc b4d0bdb52694 > src/arch/sparc/ua2005.cc b4d0bdb52694 > src/arch/sparc/utility.hh b4d0bdb52694 > src/arch/x86/mmapped_ipr.hh b4d0bdb52694 > src/arch/x86/utility.cc b4d0bdb52694 > src/base/types.hh b4d0bdb52694 > src/cpu/BaseCPU.py b4d0bdb52694 > src/cpu/base.hh b4d0bdb52694 > src/cpu/checker/thread_context.hh b4d0bdb52694 > src/cpu/inorder/cpu.hh b4d0bdb52694 > src/cpu/inorder/cpu.cc b4d0bdb52694 > src/cpu/inorder/pipeline_stage.cc b4d0bdb52694 > src/cpu/inorder/resource.hh b4d0bdb52694 > src/cpu/inorder/resource.cc b4d0bdb52694 > src/cpu/inorder/resource_pool.hh b4d0bdb52694 > src/cpu/inorder/resource_pool.cc b4d0bdb52694 > src/cpu/inorder/resources/agen_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/agen_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/branch_predictor.hh b4d0bdb52694 > src/cpu/inorder/resources/branch_predictor.cc b4d0bdb52694 > src/cpu/inorder/resources/cache_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/cache_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/decode_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/decode_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/execution_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/execution_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/fetch_seq_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/fetch_seq_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/fetch_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/fetch_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/graduation_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/graduation_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/inst_buffer.hh b4d0bdb52694 > src/cpu/inorder/resources/inst_buffer.cc b4d0bdb52694 > src/cpu/inorder/resources/mem_dep_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/mult_div_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/mult_div_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/tlb_unit.hh b4d0bdb52694 > src/cpu/inorder/resources/tlb_unit.cc b4d0bdb52694 > src/cpu/inorder/resources/use_def.hh b4d0bdb52694 > src/cpu/inorder/resources/use_def.cc b4d0bdb52694 > src/cpu/inorder/thread_context.hh b4d0bdb52694 > src/cpu/inorder/thread_context.cc b4d0bdb52694 > src/cpu/o3/commit.hh b4d0bdb52694 > src/cpu/o3/cpu.hh b4d0bdb52694 > src/cpu/o3/cpu.cc b4d0bdb52694 > src/cpu/o3/fetch_impl.hh b4d0bdb52694 > src/cpu/o3/inst_queue_impl.hh b4d0bdb52694 > src/cpu/o3/lsq_unit.hh b4d0bdb52694 > src/cpu/o3/thread_context.hh b4d0bdb52694 > src/cpu/o3/thread_context_impl.hh b4d0bdb52694 > src/cpu/simple/atomic.hh b4d0bdb52694 > src/cpu/simple/atomic.cc b4d0bdb52694 > src/cpu/simple/timing.hh b4d0bdb52694 > src/cpu/simple/timing.cc b4d0bdb52694 > src/cpu/simple_thread.hh b4d0bdb52694 > src/cpu/simple_thread.cc b4d0bdb52694 > src/cpu/testers/memtest/memtest.cc b4d0bdb52694 > src/cpu/testers/networktest/networktest.cc b4d0bdb52694 > src/cpu/thread_context.hh b4d0bdb52694 > src/dev/arm/pl111.cc b4d0bdb52694 > src/dev/i8254xGBe.cc b4d0bdb52694 > src/dev/sinic.cc b4d0bdb52694 > src/python/m5/params.py b4d0bdb52694 > src/sim/clocked_object.hh PRE-CREATION > src/sim/process.cc b4d0bdb52694 > src/sim/pseudo_inst.cc b4d0bdb52694 > > Diff: http://reviews.gem5.org/r/1338/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
