----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1338/ -----------------------------------------------------------
(Updated Aug. 8, 2012, 9:58 a.m.) Review request for Default. Description (updated) ------- Changeset 9152:6ecd7b9ddc93 --------------------------- Clock: Add a CycleCount wrapper class and use where applicable This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (or rather cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.CycleCount. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a TickCount along with suitable operators for all these classes. Diffs (updated) ----- src/arch/alpha/mmapped_ipr.hh a61fdbbc1d45 src/arch/alpha/utility.hh a61fdbbc1d45 src/arch/arm/mmapped_ipr.hh a61fdbbc1d45 src/arch/arm/table_walker.cc a61fdbbc1d45 src/arch/arm/utility.hh a61fdbbc1d45 src/arch/mips/isa.hh a61fdbbc1d45 src/arch/mips/isa.cc a61fdbbc1d45 src/arch/mips/mmapped_ipr.hh a61fdbbc1d45 src/arch/mips/mt.hh a61fdbbc1d45 src/arch/mips/utility.cc a61fdbbc1d45 src/arch/power/mmapped_ipr.hh a61fdbbc1d45 src/arch/power/utility.hh a61fdbbc1d45 src/arch/sparc/mmapped_ipr.hh a61fdbbc1d45 src/arch/sparc/tlb.hh a61fdbbc1d45 src/arch/sparc/tlb.cc a61fdbbc1d45 src/arch/sparc/ua2005.cc a61fdbbc1d45 src/arch/sparc/utility.hh a61fdbbc1d45 src/arch/x86/mmapped_ipr.hh a61fdbbc1d45 src/arch/x86/utility.cc a61fdbbc1d45 src/base/types.hh a61fdbbc1d45 src/cpu/BaseCPU.py a61fdbbc1d45 src/cpu/base.hh a61fdbbc1d45 src/cpu/checker/thread_context.hh a61fdbbc1d45 src/cpu/inorder/cpu.hh a61fdbbc1d45 src/cpu/inorder/cpu.cc a61fdbbc1d45 src/cpu/inorder/pipeline_stage.cc a61fdbbc1d45 src/cpu/inorder/resource.hh a61fdbbc1d45 src/cpu/inorder/resource.cc a61fdbbc1d45 src/cpu/inorder/resource_pool.hh a61fdbbc1d45 src/cpu/inorder/resource_pool.cc a61fdbbc1d45 src/cpu/inorder/resources/agen_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/agen_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/branch_predictor.hh a61fdbbc1d45 src/cpu/inorder/resources/branch_predictor.cc a61fdbbc1d45 src/cpu/inorder/resources/cache_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/cache_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/decode_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/decode_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/execution_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/execution_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/fetch_seq_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/fetch_seq_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/fetch_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/fetch_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/graduation_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/graduation_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/inst_buffer.hh a61fdbbc1d45 src/cpu/inorder/resources/inst_buffer.cc a61fdbbc1d45 src/cpu/inorder/resources/mem_dep_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/mult_div_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/mult_div_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/tlb_unit.hh a61fdbbc1d45 src/cpu/inorder/resources/tlb_unit.cc a61fdbbc1d45 src/cpu/inorder/resources/use_def.hh a61fdbbc1d45 src/cpu/inorder/resources/use_def.cc a61fdbbc1d45 src/cpu/inorder/thread_context.hh a61fdbbc1d45 src/cpu/inorder/thread_context.cc a61fdbbc1d45 src/cpu/o3/commit.hh a61fdbbc1d45 src/cpu/o3/cpu.hh a61fdbbc1d45 src/cpu/o3/cpu.cc a61fdbbc1d45 src/cpu/o3/fetch_impl.hh a61fdbbc1d45 src/cpu/o3/inst_queue_impl.hh a61fdbbc1d45 src/cpu/o3/lsq_unit.hh a61fdbbc1d45 src/cpu/o3/thread_context.hh a61fdbbc1d45 src/cpu/o3/thread_context_impl.hh a61fdbbc1d45 src/cpu/simple/atomic.hh a61fdbbc1d45 src/cpu/simple/atomic.cc a61fdbbc1d45 src/cpu/simple/timing.hh a61fdbbc1d45 src/cpu/simple/timing.cc a61fdbbc1d45 src/cpu/simple_thread.hh a61fdbbc1d45 src/cpu/simple_thread.cc a61fdbbc1d45 src/cpu/testers/memtest/memtest.cc a61fdbbc1d45 src/cpu/testers/networktest/networktest.cc a61fdbbc1d45 src/cpu/thread_context.hh a61fdbbc1d45 src/dev/arm/pl111.cc a61fdbbc1d45 src/dev/i8254xGBe.cc a61fdbbc1d45 src/dev/sinic.cc a61fdbbc1d45 src/python/m5/params.py a61fdbbc1d45 src/sim/clocked_object.hh PRE-CREATION src/sim/process.cc a61fdbbc1d45 src/sim/pseudo_inst.cc a61fdbbc1d45 Diff: http://reviews.gem5.org/r/1338/diff/ Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
