Hey everyone, I've found a pretty major bug in the Ruby memory controller that everyone should be aware of:
Back when the Ruby memory controller used the Ruby event queue interface (prior to changeset 8937:225590437eb2), the mem_bus_cycle_multiplier was used as the number of Ruby cycles before the memory controller should by cycled. For example, if set to 10 (the default), the memory controller would cycle every 10 Ruby cycles, and by default the Ruby clock was set to 2GHz, so a multiplier of 10 would mean that the memory controller has an effective frequency of 200MHz. In changeset 8937:225590437eb2, the memory controller was switched over to using the gem5 event queue interface, which uses ticks for scheduling events. Despite the change from Ruby cycles to ticks for scheduling, the memory controller was still scheduling cycle events based on this multiplier value, simply adding it to the current tick. Going back to our example of a multiplier of 10, this means that the memory controller would be cycled every 10 ticks or at an effective frequency of 100GHz if a tick is 1ps. I wanted to give everyone a head's up about this bug, since I haven't seen anything on the email list previously. I'm currently working on a fix, which I should have ready for review later today. Joel -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Wisconsin - Madison http://www.cs.utexas.edu/~hestness _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
