Hi Nate, It is not a tester, it is a stimuli generator for the memory system. That said, I am happy to move it if that makes more sense. (We are using it to create regressions for the memory controller though, but that is simply because it is the easiest way to generate traffic.)
There is nothing (as far as I know) that currently can simply generate "traffic" with the kind of patterns that are useful for studying interconnect and memory controller behaviour. Input is welcome. Andreas -----Original Message----- From: [email protected] [mailto:[email protected]] On Behalf Of nathan binkert Sent: 24 August 2012 19:46 To: gem5 Developer List Cc: Andreas Hansson Subject: Re: [gem5-dev] Review Request: TrafficGen: Add a basic traffic generator How is this different from the stuff in src/cpu/testers? And shouldn't this go in src/cpu/testers? Nate On Fri, Aug 24, 2012 at 11:20 AM, Andreas Hansson <[email protected]> wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1368/ > ----------------------------------------------------------- > > Review request for Default. > > > Description > ------- > > Changeset 9170:bfab7266331f > --------------------------- > TrafficGen: Add a basic traffic generator > > This patch adds a traffic generator to the code base. The generator is > aimed to be used as a black box model to create appropriate use-cases > and benchmarks for the memory system, and in particular the > interconnect and the memory controller. > > The traffic generator is a master module, where the actual behaviour > is captured in a state-transition graph where each state generates > some sort of traffic. By constructing a graph it is possible to create > very elaborate scenarios from basic generators. Currencly the set of > generators include idling, linear address sweeps, random address > sequences and playback of traces (recording will be done by the > Communication Monitor in a follow-up patch). At the moment the graph > and the states are described in an ad-hoc line-based format, and in > the future this should be aligned with our used of e.g. the Google > protobufs. Similarly for the traces, the format is currently a > simplistic ad-hoc line-based format that merely serves as a starting > point. > > In addition to being used as a black-box model for system components, > the traffic generator is also useful for creating test cases and > regressions for the interconnect and memory system. In future patches > we will use the traffic generator to create DRAM test cases for the > controller model. > > The patch following this one adds a basic regressions which also > contains an example configuration script and trace file for playback. > > > Diffs > ----- > > src/mem/SConscript 1d983855df2c > src/mem/TrafficGen.py PRE-CREATION > src/mem/traffic_gen.hh PRE-CREATION > src/mem/traffic_gen.cc PRE-CREATION > > Diff: http://reviews.gem5.org/r/1368/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
