changeset 9b6882b58a3f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9b6882b58a3f
description:
Clock: Inherit the clock from parent by default
This patch changes the default 1 Tick clock period to a proxy that
resolves the parents clock. As a result of this, the caches and
L1-to-L2 bus, for example, will automatically use the clock period of
the CPU unless explicitly overridden.
To ensure backwards compatibility, the System class overrides the
proxy and specifies a 1 Tick clock. We could change this to something
more reasonable in a follow-on patch, perhaps 1 GHz or something
similar.
With this patch applied, all clocked objects should have a reasonable
clock period set, and could start specifying delays in Cycles instead
of absolute time.
diffstat:
src/sim/ClockedObject.py | 6 +++++-
src/sim/System.py | 7 +++++++
2 files changed, 12 insertions(+), 1 deletions(-)
diffs (35 lines):
diff -r fda147c035b3 -r 9b6882b58a3f src/sim/ClockedObject.py
--- a/src/sim/ClockedObject.py Mon Oct 15 08:07:06 2012 -0400
+++ b/src/sim/ClockedObject.py Mon Oct 15 08:07:07 2012 -0400
@@ -37,9 +37,13 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
class ClockedObject(SimObject):
type = 'ClockedObject'
abstract = True
- clock = Param.Clock('1t', "Clock speed")
+ # Clock period of this object, with the default value being the
+ # clock period of the parent object, unproxied at instantiation
+ # time
+ clock = Param.Clock(Parent.clock, "Clock speed")
diff -r fda147c035b3 -r 9b6882b58a3f src/sim/System.py
--- a/src/sim/System.py Mon Oct 15 08:07:06 2012 -0400
+++ b/src/sim/System.py Mon Oct 15 08:07:07 2012 -0400
@@ -41,6 +41,13 @@
type = 'System'
system_port = MasterPort("System port")
+ # Override the clock from the ClockedObject which looks at the
+ # parent clock by default
+ clock = '1t'
+ # @todo Either make this value 0 and treat it as an error if it is
+ # not overridden, or choose a more sensible value in the range of
+ # 1GHz
+
@classmethod
def export_method_cxx_predecls(cls, code):
code('#include "sim/system.hh"')
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