changeset ac627fdc8991 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ac627fdc8991
description:
Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.
The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.
The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache.
diffstat:
tests/configs/pc-o3-timing.py | 29 +++++++++++++----------------
tests/configs/pc-simple-atomic.py | 29 +++++++++++++----------------
tests/configs/pc-simple-timing.py | 26 +++++++++++---------------
tests/configs/realview-o3-checker.py | 27 ++++++++++++---------------
tests/configs/realview-o3.py | 22 +++++++++-------------
tests/configs/realview-simple-atomic.py | 25 +++++++++++--------------
tests/configs/realview-simple-timing.py | 22 +++++++++-------------
tests/configs/tsunami-inorder.py | 24 +++++++++++-------------
tests/configs/tsunami-o3.py | 22 +++++++++-------------
tests/configs/tsunami-simple-atomic.py | 25 +++++++++++--------------
tests/configs/tsunami-simple-timing.py | 22 +++++++++-------------
11 files changed, 118 insertions(+), 155 deletions(-)
diffs (truncated from 446 to 300 lines):
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/pc-o3-timing.py Mon Oct 15 08:07:09 2012 -0400
@@ -90,28 +90,25 @@
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
+
+system.cpu = cpu
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- PageTableWalkerCache(),
- PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8),
+ PageTableWalkerCache(),
+ PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/pc-simple-atomic.py Mon Oct 15 08:07:09 2012 -0400
@@ -92,28 +92,25 @@
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
+
+system.cpu = cpu
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- PageTableWalkerCache(),
- PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8),
+ PageTableWalkerCache(),
+ PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/pc-simple-timing.py Mon Oct 15 08:07:09 2012 -0400
@@ -93,27 +93,23 @@
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- PageTableWalkerCache(),
- PageTableWalkerCache())
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8),
+ PageTableWalkerCache(),
+ PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/realview-o3-checker.py
--- a/tests/configs/realview-o3-checker.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/realview-o3-checker.py Mon Oct 15 08:07:09 2012 -0400
@@ -85,26 +85,23 @@
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+#connect up the checker
+cpu.addCheckerCpu()
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the checker
-cpu.addCheckerCpu()
-#connect up the cpu and l1s
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8))
+# create the interrupt controller
cpu.createInterruptController()
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/realview-o3.py Mon Oct 15 08:07:09 2012 -0400
@@ -76,25 +76,21 @@
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/realview-simple-atomic.py Mon Oct 15 08:07:09 2012 -0400
@@ -73,26 +73,23 @@
cpu = AtomicSimpleCPU(cpu_id=0)
#the system
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
+
+system.cpu = cpu
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/realview-simple-timing.py Mon Oct 15 08:07:09 2012 -0400
@@ -76,25 +76,21 @@
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
+
+#create the iocache
system.iocache = IOCache()
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
-
-#connect up the l2 cache
-system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-system.l2c.mem_side = system.membus.slave
-
-#connect up the cpu and l1s
-cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4))
+#connect up the cpu and caches
+cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
+ L1(size = '32kB', assoc = 4),
+ L2(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
-# connect cpu level-1 caches to shared level-2 cache
-cpu.connectAllPorts(system.toL2Bus, system.membus)
+# connect cpu and caches to the rest of the system
+cpu.connectAllPorts(system.membus)
+# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
diff -r 9b6882b58a3f -r ac627fdc8991 tests/configs/tsunami-inorder.py
--- a/tests/configs/tsunami-inorder.py Mon Oct 15 08:07:07 2012 -0400
+++ b/tests/configs/tsunami-inorder.py Mon Oct 15 08:07:09 2012 -0400
@@ -80,23 +80,21 @@
system = FSConfig.makeLinuxAlphaSystem('timing')
system.cpu = cpu
-#create the l1/l2 bus
-system.toL2Bus = CoherentBus()
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