changeset aa7bf10e822a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa7bf10e822a
description:
config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.
The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.
As only regressions that shared the same cache configuration are
updated, no regressions are affected.
diffstat:
configs/common/Caches.py | 36 +++++++++++-------
tests/configs/o3-timing-mp.py | 25 +------------
tests/configs/pc-o3-timing.py | 53 +-------------------------
tests/configs/pc-simple-atomic.py | 55 +--------------------------
tests/configs/pc-simple-timing.py | 54 +--------------------------
tests/configs/realview-o3-checker.py | 42 +--------------------
tests/configs/realview-o3-dual.py | 41 +-------------------
tests/configs/realview-o3.py | 42 +--------------------
tests/configs/realview-simple-atomic-dual.py | 41 +-------------------
tests/configs/realview-simple-atomic.py | 41 +-------------------
tests/configs/realview-simple-timing-dual.py | 41 +-------------------
tests/configs/realview-simple-timing.py | 42 +--------------------
tests/configs/tsunami-inorder.py | 43 +--------------------
tests/configs/tsunami-o3-dual.py | 43 +--------------------
tests/configs/tsunami-o3.py | 43 +--------------------
tests/configs/tsunami-simple-atomic-dual.py | 42 +--------------------
tests/configs/tsunami-simple-atomic.py | 42 +--------------------
tests/configs/tsunami-simple-timing-dual.py | 42 +--------------------
tests/configs/tsunami-simple-timing.py | 43 +--------------------
19 files changed, 57 insertions(+), 754 deletions(-)
diffs (truncated from 1135 to 300 lines):
diff -r 10cf9d9fe5ed -r aa7bf10e822a configs/common/Caches.py
--- a/configs/common/Caches.py Thu Oct 25 04:32:42 2012 -0400
+++ b/configs/common/Caches.py Thu Oct 25 04:32:44 2012 -0400
@@ -40,22 +40,40 @@
from m5.objects import *
-class L1Cache(BaseCache):
+# Base implementations of L1, L2, IO and TLB-walker caches. There are
+# used in the regressions and also as base components in the
+# system-configuration scripts. The values are meant to serve as a
+# starting point, and specific parameters can be overridden in the
+# specific instantiations.
+
+class L1(BaseCache):
assoc = 2
- block_size = 64
hit_latency = 2
response_latency = 2
- mshrs = 10
+ block_size = 64
+ mshrs = 4
tgts_per_mshr = 20
is_top_level = True
-class L2Cache(BaseCache):
+class L2(BaseCache):
assoc = 8
block_size = 64
hit_latency = 20
response_latency = 20
+ mshrs = 92
+ tgts_per_mshr = 16
+ write_buffers = 8
+
+class IOCache(BaseCache):
+ assoc = 8
+ block_size = 64
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
+ size = '1kB'
tgts_per_mshr = 12
+ forward_snoops = False
+ is_top_level = True
class PageTableWalkerCache(BaseCache):
assoc = 2
@@ -67,13 +85,3 @@
tgts_per_mshr = 12
is_top_level = True
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- forward_snoops = False
- is_top_level = True
diff -r 10cf9d9fe5ed -r aa7bf10e822a tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Thu Oct 25 04:32:42 2012 -0400
+++ b/tests/configs/o3-timing-mp.py Thu Oct 25 04:32:44 2012 -0400
@@ -29,30 +29,7 @@
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
+from Caches import *
nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
diff -r 10cf9d9fe5ed -r aa7bf10e822a tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Thu Oct 25 04:32:42 2012 -0400
+++ b/tests/configs/pc-o3-timing.py Thu Oct 25 04:32:44 2012 -0400
@@ -31,59 +31,10 @@
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
+from Caches import *
mem_size = '128MB'
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 20
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- size = '1kB'
- tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size=mem_size)]
- forward_snoops = False
-
#cpu
cpu = DerivO3CPU(cpu_id=0)
#the system
@@ -94,7 +45,7 @@
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff -r 10cf9d9fe5ed -r aa7bf10e822a tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py Thu Oct 25 04:32:42 2012 -0400
+++ b/tests/configs/pc-simple-atomic.py Thu Oct 25 04:32:44 2012 -0400
@@ -31,61 +31,10 @@
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
+from Caches import *
mem_size = '128MB'
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- size = '1kB'
- tgts_per_mshr = 12
- is_top_level = True
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size=mem_size)]
- forward_snoops = False
- is_top_level = True
-
#cpu
cpu = AtomicSimpleCPU(cpu_id=0)
#the system
@@ -96,7 +45,7 @@
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
diff -r 10cf9d9fe5ed -r aa7bf10e822a tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py Thu Oct 25 04:32:42 2012 -0400
+++ b/tests/configs/pc-simple-timing.py Thu Oct 25 04:32:44 2012 -0400
@@ -31,60 +31,10 @@
m5.util.addToPath('../configs/common')
from Benchmarks import SysConfig
import FSConfig
-
+from Caches import *
mem_size = '128MB'
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
- assoc = 2
- block_size = 64
- hit_latency = 2
- response_latency = 2
- mshrs = 10
- size = '1kB'
- tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
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