changeset 227d19399b51 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=227d19399b51
description:
config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).
Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.
This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
diffstat:
configs/common/FSConfig.py | 16 ++++++++--------
tests/configs/inorder-timing.py | 2 +-
tests/configs/o3-timing-checker.py | 2 +-
tests/configs/o3-timing-mp.py | 2 +-
tests/configs/o3-timing.py | 2 +-
5 files changed, 12 insertions(+), 12 deletions(-)
diffs (117 lines):
diff -r aa7bf10e822a -r 227d19399b51 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Thu Oct 25 04:32:44 2012 -0400
+++ b/configs/common/FSConfig.py Thu Oct 25 13:14:38 2012 -0400
@@ -73,7 +73,7 @@
# base address (including the PCI config space)
self.bridge = Bridge(delay='50ns',
ranges = [AddrRange(IO_address_space_base, Addr.max)])
- self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
+ self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.physmem.port = self.membus.master
@@ -109,7 +109,7 @@
ide = IdeController(disks=[Parent.disk0, Parent.disk2],
pci_func=0, pci_dev=0, pci_bus=0)
- physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
+ physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
self = LinuxAlphaSystem(physmem = physmem)
if not mdesc:
# generic system
@@ -178,9 +178,9 @@
self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
- self.physmem = SimpleMemory(range = AddrRange(Addr('1MB'), size = '64MB'),
+ self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'),
zero = True)
- self.physmem2 = SimpleMemory(range = AddrRange(Addr('2GB'), size ='256MB'),
+ self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'),
zero = True)
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
@@ -271,7 +271,7 @@
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
+ self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())),
zero = True)
else:
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
@@ -285,7 +285,7 @@
boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
- self.physmem = SimpleMemory(range =
+ self.physmem = SimpleDRAM(range =
AddrRange(self.realview.mem_start_addr,
size = mdesc.mem()),
conf_table_reported = True)
@@ -323,7 +323,7 @@
self.iobus = NoncoherentBus()
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
- self.physmem = SimpleMemory(range = AddrRange('1GB'))
+ self.physmem = SimpleDRAM(range = AddrRange('1GB'))
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.physmem.port = self.membus.master
@@ -428,7 +428,7 @@
self.mem_mode = mem_mode
# Physical memory
- self.physmem = SimpleMemory(range = AddrRange(mdesc.mem()))
+ self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
# Platform
self.pc = Pc()
diff -r aa7bf10e822a -r 227d19399b51 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Thu Oct 25 04:32:44 2012 -0400
+++ b/tests/configs/inorder-timing.py Thu Oct 25 13:14:38 2012 -0400
@@ -50,7 +50,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleMemory(),
+ physmem = SimpleDRAM(),
membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff -r aa7bf10e822a -r 227d19399b51 tests/configs/o3-timing-checker.py
--- a/tests/configs/o3-timing-checker.py Thu Oct 25 04:32:44 2012 -0400
+++ b/tests/configs/o3-timing-checker.py Thu Oct 25 13:14:38 2012 -0400
@@ -63,7 +63,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleMemory(),
+ physmem = SimpleDRAM(),
membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
diff -r aa7bf10e822a -r 227d19399b51 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Thu Oct 25 04:32:44 2012 -0400
+++ b/tests/configs/o3-timing-mp.py Thu Oct 25 13:14:38 2012 -0400
@@ -35,7 +35,7 @@
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
+system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
diff -r aa7bf10e822a -r 227d19399b51 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Thu Oct 25 04:32:44 2012 -0400
+++ b/tests/configs/o3-timing.py Thu Oct 25 13:14:38 2012 -0400
@@ -52,7 +52,7 @@
cpu.clock = '2GHz'
system = System(cpu = cpu,
- physmem = SimpleMemory(),
+ physmem = SimpleDRAM(),
membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
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