changeset 0548b3e9734d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0548b3e9734d
description:
cpu: Implement a flat register interface in thread contexts
Some architectures map registers differently depending on their mode
of operations. There is currently no architecture independent way of
accessing all registers. This patch introduces a flat register
interface to the ThreadContext class. This interface is useful, for
example, when serializing or copying thread contexts.
diffstat:
src/cpu/checker/thread_context.hh | 20 +++++++++++++-
src/cpu/inorder/thread_context.cc | 55 +++++++++++++++++++++++++++++++++++++++
src/cpu/inorder/thread_context.hh | 21 ++++++++++++++
src/cpu/o3/thread_context.hh | 34 +++++++++++++++++++----
src/cpu/o3/thread_context_impl.hh | 20 ++++---------
src/cpu/simple_thread.hh | 24 ++++++++++++----
src/cpu/thread_context.hh | 42 +++++++++++++++++++++++++++++
7 files changed, 189 insertions(+), 27 deletions(-)
diffs (truncated from 404 to 300 lines):
diff -r a24092160ec7 -r 0548b3e9734d src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Mon Jan 07 13:05:42 2013 -0500
+++ b/src/cpu/checker/thread_context.hh Mon Jan 07 13:05:44 2013 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -302,6 +302,24 @@
bool misspeculating() { return actualTC->misspeculating(); }
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
+
+ uint64_t readIntRegFlat(int idx)
+ { return actualTC->readIntRegFlat(idx); }
+
+ void setIntRegFlat(int idx, uint64_t val)
+ { actualTC->setIntRegFlat(idx, val); }
+
+ FloatReg readFloatRegFlat(int idx)
+ { return actualTC->readFloatRegFlat(idx); }
+
+ void setFloatRegFlat(int idx, FloatReg val)
+ { actualTC->setFloatRegFlat(idx, val); }
+
+ FloatRegBits readFloatRegBitsFlat(int idx)
+ { return actualTC->readFloatRegBitsFlat(idx); }
+
+ void setFloatRegBitsFlat(int idx, FloatRegBits val)
+ { actualTC->setFloatRegBitsFlat(idx, val); }
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff -r a24092160ec7 -r 0548b3e9734d src/cpu/inorder/thread_context.cc
--- a/src/cpu/inorder/thread_context.cc Mon Jan 07 13:05:42 2013 -0500
+++ b/src/cpu/inorder/thread_context.cc Mon Jan 07 13:05:44 2013 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
@@ -249,3 +261,46 @@
{
cpu->setMiscReg(misc_reg, val, thread->threadId());
}
+
+
+uint64_t
+InOrderThreadContext::readIntRegFlat(int idx)
+{
+ const ThreadID tid = thread->threadId();
+ return cpu->readIntReg(idx, tid);
+}
+
+void
+InOrderThreadContext::setIntRegFlat(int idx, uint64_t val)
+{
+ const ThreadID tid = thread->threadId();
+ cpu->setIntReg(idx, val, tid);
+}
+
+FloatReg
+InOrderThreadContext::readFloatRegFlat(int idx)
+{
+ const ThreadID tid = thread->threadId();
+ return cpu->readFloatReg(idx, tid);
+}
+
+void
+InOrderThreadContext::setFloatRegFlat(int idx, FloatReg val)
+{
+ const ThreadID tid = thread->threadId();
+ cpu->setFloatReg(idx, val, tid);
+}
+
+FloatRegBits
+InOrderThreadContext::readFloatRegBitsFlat(int idx)
+{
+ const ThreadID tid = thread->threadId();
+ return cpu->readFloatRegBits(idx, tid);
+}
+
+void
+InOrderThreadContext::setFloatRegBitsFlat(int idx, FloatRegBits val)
+{
+ const ThreadID tid = thread->threadId();
+ cpu->setFloatRegBits(idx, val, tid);
+}
diff -r a24092160ec7 -r 0548b3e9734d src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh Mon Jan 07 13:05:42 2013 -0500
+++ b/src/cpu/inorder/thread_context.hh Mon Jan 07 13:05:44 2013 -0500
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
@@ -292,6 +304,15 @@
void changeRegFileContext(unsigned param,
unsigned val)
{ panic("Not supported!"); }
+
+ uint64_t readIntRegFlat(int idx);
+ void setIntRegFlat(int idx, uint64_t val);
+
+ FloatReg readFloatRegFlat(int idx);
+ void setFloatRegFlat(int idx, FloatReg val);
+
+ FloatRegBits readFloatRegBitsFlat(int idx);
+ void setFloatRegBitsFlat(int idx, FloatRegBits val);
};
#endif
diff -r a24092160ec7 -r 0548b3e9734d src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Mon Jan 07 13:05:42 2013 -0500
+++ b/src/cpu/o3/thread_context.hh Mon Jan 07 13:05:44 2013 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -175,18 +175,30 @@
virtual void clearArchRegs();
/** Reads an integer register. */
- virtual uint64_t readIntReg(int reg_idx);
+ virtual uint64_t readIntReg(int reg_idx) {
+ return readIntRegFlat(flattenIntIndex(reg_idx));
+ }
- virtual FloatReg readFloatReg(int reg_idx);
+ virtual FloatReg readFloatReg(int reg_idx) {
+ return readFloatRegFlat(flattenFloatIndex(reg_idx));
+ }
- virtual FloatRegBits readFloatRegBits(int reg_idx);
+ virtual FloatRegBits readFloatRegBits(int reg_idx) {
+ return readFloatRegBitsFlat(flattenFloatIndex(reg_idx));
+ }
/** Sets an integer register to a value. */
- virtual void setIntReg(int reg_idx, uint64_t val);
+ virtual void setIntReg(int reg_idx, uint64_t val) {
+ setIntRegFlat(flattenIntIndex(reg_idx), val);
+ }
- virtual void setFloatReg(int reg_idx, FloatReg val);
+ virtual void setFloatReg(int reg_idx, FloatReg val) {
+ setFloatRegFlat(flattenFloatIndex(reg_idx), val);
+ }
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
+ virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
+ setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val);
+ }
/** Reads this thread's PC state. */
virtual TheISA::PCState pcState()
@@ -268,6 +280,14 @@
cpu->squashFromTC(thread->threadId());
}
+ virtual uint64_t readIntRegFlat(int idx);
+ virtual void setIntRegFlat(int idx, uint64_t val);
+
+ virtual FloatReg readFloatRegFlat(int idx);
+ virtual void setFloatRegFlat(int idx, FloatReg val);
+
+ virtual FloatRegBits readFloatRegBitsFlat(int idx);
+ virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
};
#endif
diff -r a24092160ec7 -r 0548b3e9734d src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Mon Jan 07 13:05:42 2013 -0500
+++ b/src/cpu/o3/thread_context_impl.hh Mon Jan 07 13:05:44 2013 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -224,33 +224,29 @@
template <class Impl>
uint64_t
-O3ThreadContext<Impl>::readIntReg(int reg_idx)
+O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
{
- reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
return cpu->readArchIntReg(reg_idx, thread->threadId());
}
template <class Impl>
TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatReg(int reg_idx)
+O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
{
- reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
return cpu->readArchFloatReg(reg_idx, thread->threadId());
}
template <class Impl>
TheISA::FloatRegBits
-O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
+O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
{
- reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
}
template <class Impl>
void
-O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
+O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, uint64_t val)
{
- reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
cpu->setArchIntReg(reg_idx, val, thread->threadId());
conditionalSquash();
@@ -258,9 +254,8 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
+O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
{
- reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
cpu->setArchFloatReg(reg_idx, val, thread->threadId());
conditionalSquash();
@@ -268,9 +263,8 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
+O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
{
- reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
conditionalSquash();
diff -r a24092160ec7 -r 0548b3e9734d src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Mon Jan 07 13:05:42 2013 -0500
+++ b/src/cpu/simple_thread.hh Mon Jan 07 13:05:44 2013 -0500
@@ -237,7 +237,7 @@
{
int flatIndex = isa->flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
- uint64_t regVal = intRegs[flatIndex];
+ uint64_t regVal(readIntRegFlat(flatIndex));
DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
reg_idx, flatIndex, regVal);
return regVal;
@@ -247,7 +247,7 @@
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatReg regVal = floatRegs.f[flatIndex];
+ FloatReg regVal(readFloatRegFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
return regVal;
@@ -257,7 +257,7 @@
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
assert(flatIndex < TheISA::NumFloatRegs);
- FloatRegBits regVal = floatRegs.i[flatIndex];
+ FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
return regVal;
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
