changeset ddf45c1d54d4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ddf45c1d54d4
description:
cpu: Initialize the O3 pipeline from startup()
The entire O3 pipeline used to be initialized from init(), which is
called before initState() or unserialize(). This causes the pipeline
to be initialized from an incorrect thread context. This doesn't
currently lead to correctness problems as instructions fetched from
the incorrect start PC will be squashed a few cycles after
initialization.
This patch will affect the regressions since the O3 CPU now issues its
first instruction fetch to the correct PC instead of 0x0.
diffstat:
src/cpu/o3/commit.hh | 2 +-
src/cpu/o3/commit_impl.hh | 4 ++--
src/cpu/o3/cpu.cc | 16 ++++++++++------
src/cpu/o3/cpu.hh | 2 ++
src/cpu/o3/fetch.hh | 2 +-
src/cpu/o3/fetch_impl.hh | 2 +-
src/cpu/o3/iew.hh | 2 +-
src/cpu/o3/iew_impl.hh | 4 ++--
src/cpu/o3/rename.hh | 2 +-
src/cpu/o3/rename_impl.hh | 4 ++--
10 files changed, 23 insertions(+), 17 deletions(-)
diffs (160 lines):
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/commit.hh Mon Jan 07 13:05:44 2013 -0500
@@ -195,7 +195,7 @@
void setROB(ROB *rob_ptr);
/** Initializes stage by sending back the number of free entries. */
- void initStage();
+ void startupStage();
/** Initializes the draining of commit. */
bool drain();
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/commit_impl.hh Mon Jan 07 13:05:44 2013 -0500
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -348,7 +348,7 @@
template <class Impl>
void
-DefaultCommit<Impl>::initStage()
+DefaultCommit<Impl>::startupStage()
{
rob->setActiveThreads(activeThreads);
rob->resetEntries();
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/cpu.cc Mon Jan 07 13:05:44 2013 -0500
@@ -679,13 +679,17 @@
for (int tid = 0; tid < numThreads; ++tid)
thread[tid]->noSquashFromTC = false;
- // Initialize stages.
- fetch.initStage();
- iew.initStage();
- rename.initStage();
- commit.initStage();
+ commit.setThreads(thread);
+}
- commit.setThreads(thread);
+template <class Impl>
+void
+FullO3CPU<Impl>::startup()
+{
+ fetch.startupStage();
+ iew.startupStage();
+ rename.startupStage();
+ commit.startupStage();
}
template <class Impl>
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/cpu.hh Mon Jan 07 13:05:44 2013 -0500
@@ -369,6 +369,8 @@
/** Initialize the CPU */
void init();
+ void startup();
+
/** Returns the Number of Active Threads in the CPU */
int numActiveThreads()
{ return activeThreads.size(); }
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/fetch.hh Mon Jan 07 13:05:44 2013 -0500
@@ -215,7 +215,7 @@
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
/** Initialize stage. */
- void initStage();
+ void startupStage();
/** Tells the fetch stage that the Icache is set. */
void setIcache();
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/fetch_impl.hh Mon Jan 07 13:05:44 2013 -0500
@@ -302,7 +302,7 @@
template<class Impl>
void
-DefaultFetch<Impl>::initStage()
+DefaultFetch<Impl>::startupStage()
{
// Setup PC and nextPC with initial state.
for (ThreadID tid = 0; tid < numThreads; tid++) {
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/iew.hh Mon Jan 07 13:05:44 2013 -0500
@@ -133,7 +133,7 @@
void regStats();
/** Initializes stage; sends back the number of free IQ and LSQ entries. */
- void initStage();
+ void startupStage();
/** Sets main time buffer used for backwards communication. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/iew_impl.hh Mon Jan 07 13:05:44 2013 -0500
@@ -283,7 +283,7 @@
template<class Impl>
void
-DefaultIEW<Impl>::initStage()
+DefaultIEW<Impl>::startupStage()
{
for (ThreadID tid = 0; tid < numThreads; tid++) {
toRename->iewInfo[tid].usedIQ = true;
@@ -408,7 +408,7 @@
ldstQueue.takeOverFrom();
fuPool->takeOver();
- initStage();
+ startupStage();
cpu->activityThisCycle();
for (ThreadID tid = 0; tid < numThreads; tid++) {
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/rename.hh
--- a/src/cpu/o3/rename.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/rename.hh Mon Jan 07 13:05:44 2013 -0500
@@ -143,7 +143,7 @@
public:
/** Initializes variables for the stage. */
- void initStage();
+ void startupStage();
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<ThreadID> *at_ptr);
diff -r 0548b3e9734d -r ddf45c1d54d4 src/cpu/o3/rename_impl.hh
--- a/src/cpu/o3/rename_impl.hh Mon Jan 07 13:05:44 2013 -0500
+++ b/src/cpu/o3/rename_impl.hh Mon Jan 07 13:05:44 2013 -0500
@@ -228,7 +228,7 @@
template <class Impl>
void
-DefaultRename<Impl>::initStage()
+DefaultRename<Impl>::startupStage()
{
// Grab the number of free entries directly from the stages.
for (ThreadID tid = 0; tid < numThreads; tid++) {
@@ -317,7 +317,7 @@
DefaultRename<Impl>::takeOverFrom()
{
_status = Inactive;
- initStage();
+ startupStage();
// Reset all state prior to taking over from the other CPU.
for (ThreadID tid = 0; tid < numThreads; tid++) {
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