changeset 67a6ba6604c8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=67a6ba6604c8
description:
x86: Changes to decoder, corrects 9376
The changes made by the changeset 9376 were not quite correct. The
patch made
changes to the code which resulted in decoder not getting initialized
correctly
when the state was restored from a checkpoint.
This patch adds a startup function to each ISA object. For x86, this
function
sets the required state in the decoder. For other ISAs, the function is
empty
right now.
diffstat:
src/arch/alpha/isa.hh | 2 ++
src/arch/arm/isa.hh | 2 ++
src/arch/mips/isa.hh | 2 ++
src/arch/power/isa.hh | 2 ++
src/arch/sparc/isa.hh | 2 ++
src/arch/x86/isa.cc | 6 ++++++
src/arch/x86/isa.hh | 1 +
src/cpu/o3/cpu.cc | 3 +++
src/cpu/simple/base.cc | 7 +++++++
src/cpu/simple/base.hh | 2 ++
src/cpu/simple_thread.cc | 6 ++++++
src/cpu/simple_thread.hh | 1 +
12 files changed, 36 insertions(+), 0 deletions(-)
diffs (156 lines):
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/alpha/isa.hh Sat Jan 12 22:09:48 2013 -0600
@@ -106,6 +106,8 @@
const Params *params() const;
ISA(Params *p);
+
+ void startup(ThreadContext *tc) {}
};
}
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/arm/isa.hh Sat Jan 12 22:09:48 2013 -0600
@@ -193,6 +193,8 @@
updateRegMap(tmp_cpsr);
}
+ void startup(ThreadContext *tc) {}
+
typedef ArmISAParams Params;
const Params *params() const;
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/mips/isa.hh Sat Jan 12 22:09:48 2013 -0600
@@ -157,6 +157,8 @@
static std::string miscRegNames[NumMiscRegs];
public:
+ void startup(ThreadContext *tc) {}
+
const Params *params() const;
ISA(Params *p);
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/power/isa.hh
--- a/src/arch/power/isa.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/power/isa.hh Sat Jan 12 22:09:48 2013 -0600
@@ -98,6 +98,8 @@
return reg;
}
+ void startup(ThreadContext *tc) {}
+
const Params *params() const;
ISA(Params *p);
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/sparc/isa.hh
--- a/src/arch/sparc/isa.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/sparc/isa.hh Sat Jan 12 22:09:48 2013 -0600
@@ -171,6 +171,8 @@
void unserialize(Checkpoint *cp, const std::string & section);
+ void startup(ThreadContext *tc) {}
+
protected:
bool isHyperPriv() { return hpstate.hpriv; }
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/x86/isa.cc
--- a/src/arch/x86/isa.cc Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/x86/isa.cc Sat Jan 12 22:09:48 2013 -0600
@@ -387,6 +387,12 @@
NULL);
}
+void
+ISA::startup(ThreadContext *tc)
+{
+ tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
+}
+
}
X86ISA::ISA *
diff -r 5532a1642108 -r 67a6ba6604c8 src/arch/x86/isa.hh
--- a/src/arch/x86/isa.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/arch/x86/isa.hh Sat Jan 12 22:09:48 2013 -0600
@@ -87,6 +87,7 @@
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+ void startup(ThreadContext *tc);
};
}
diff -r 5532a1642108 -r 67a6ba6604c8 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Tue Jan 08 17:12:22 2013 -0500
+++ b/src/cpu/o3/cpu.cc Sat Jan 12 22:09:48 2013 -0600
@@ -678,6 +678,9 @@
void
FullO3CPU<Impl>::startup()
{
+ for (int tid = 0; tid < numThreads; ++tid)
+ isa[tid]->startup(threadContexts[tid]);
+
fetch.startupStage();
decode.startupStage();
iew.startupStage();
diff -r 5532a1642108 -r 67a6ba6604c8 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc Tue Jan 08 17:12:22 2013 -0500
+++ b/src/cpu/simple/base.cc Sat Jan 12 22:09:48 2013 -0600
@@ -515,6 +515,13 @@
}
}
+void
+BaseSimpleCPU::startup()
+{
+ BaseCPU::startup();
+ thread->startup();
+}
+
/*Fault
BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
{
diff -r 5532a1642108 -r 67a6ba6604c8 src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/cpu/simple/base.hh Sat Jan 12 22:09:48 2013 -0600
@@ -172,6 +172,8 @@
virtual void regStats();
virtual void resetStats();
+ virtual void startup();
+
// number of simulated instructions
Counter numInst;
Counter startNumInst;
diff -r 5532a1642108 -r 67a6ba6604c8 src/cpu/simple_thread.cc
--- a/src/cpu/simple_thread.cc Tue Jan 08 17:12:22 2013 -0500
+++ b/src/cpu/simple_thread.cc Sat Jan 12 22:09:48 2013 -0600
@@ -143,6 +143,12 @@
}
void
+SimpleThread::startup()
+{
+ isa->startup(tc);
+}
+
+void
SimpleThread::dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat",
diff -r 5532a1642108 -r 67a6ba6604c8 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Tue Jan 08 17:12:22 2013 -0500
+++ b/src/cpu/simple_thread.hh Sat Jan 12 22:09:48 2013 -0600
@@ -150,6 +150,7 @@
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
+ void startup();
/***************************************************************
* SimpleThread functions to provide CPU with access to various
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