[gem5-dev] changeset in gem5: base simple cpu: removes commented out code a...

[Nilay Vaish]

changeset 116396961ad1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=116396961ad1
description:
        base simple cpu: removes commented out code about cache ops

diffstat:

 src/cpu/simple/base.cc |  35 -----------------------------------
 1 files changed, 0 insertions(+), 35 deletions(-)

diffs (42 lines):

diff -r 67a6ba6604c8 -r 116396961ad1 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc    Sat Jan 12 22:09:48 2013 -0600
+++ b/src/cpu/simple/base.cc    Sat Jan 12 22:11:16 2013 -0600
@@ -521,38 +521,3 @@
     BaseCPU::startup();
     thread->startup();
 }
-
-/*Fault
-BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
-{
-    // translate to physical address
-    Fault fault = NoFault;
-    int CacheID = Op & 0x3; // Lower 3 bits identify Cache
-    int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
-    if(CacheID > 1)
-      {
-        warn("CacheOps not implemented for secondary/tertiary caches\n");
-      }
-    else
-      {
-        switch(CacheOP)
-          { // Fill Packet Type
-          case 0: warn("Invalidate Cache Op\n");
-            break;
-          case 1: warn("Index Load Tag Cache Op\n");
-            break;
-          case 2: warn("Index Store Tag Cache Op\n");
-            break;
-          case 4: warn("Hit Invalidate Cache Op\n");
-            break;
-          case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
-            break;
-          case 6: warn("Hit Writeback\n");
-            break;
-          case 7: warn("Fetch & Lock Cache Op\n");
-            break;
-          default: warn("Unimplemented Cache Op\n");
-          }
-      }
-    return fault;
-}*/
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