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Review request for Default. Description ------- Changeset 9634:4a87fbab0988 --------------------------- Sequencers: Reset clocks after cache warmup/cooldown Sequencers can be accessed by CPU cores after cache warm-up or cool-down but before their clocks have been reset in normal simulation, which can cause MessageBuffer assertion failures that the enqueue time of a message is later than the send time. This change ensures that the Sequencer clocks are reset after warm-up and cool-down to avoid this problem. Diffs ----- src/mem/ruby/recorder/CacheRecorder.hh fa31189e1fb5 src/mem/ruby/recorder/CacheRecorder.cc fa31189e1fb5 src/mem/ruby/system/Sequencer.hh fa31189e1fb5 src/mem/ruby/system/System.cc fa31189e1fb5 Diff: http://reviews.gem5.org/r/1817/diff/ Testing ------- Numerous checkpoint restore tests with x86 + Ruby Thanks, Joel Hestness _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
