[gem5-dev] changeset in gem5: mem: Adapt the LPDDR2 to match a single x32 c...

[Andreas Hansson]

changeset 5dd29a521cac in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5dd29a521cac
description:
        mem: Adapt the LPDDR2 to match a single x32 channel

        This patch adapts the existing LPDDR2 configuration to make use of the
        multi-channel functionality. Thus, to get a x64 interface two
        controllers should be instantiated using the makeMultiChannel method.

        The page size and ranks are also adapted to better suit with a typical
        LPDDR2 part.

diffstat:

 src/mem/SimpleDRAM.py |  24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diffs (52 lines):

diff -r 1305bec2733f -r 5dd29a521cac src/mem/SimpleDRAM.py
--- a/src/mem/SimpleDRAM.py     Thu May 30 12:53:54 2013 -0400
+++ b/src/mem/SimpleDRAM.py     Thu May 30 12:53:55 2013 -0400
@@ -203,17 +203,16 @@
     activation_limit = 4
 
 
-# High-level model of a single LPDDR2-S4 x64 interface (one
+# High-level model of a single LPDDR2-S4 x32 interface (one
 # command/address bus), with default timings based on a LPDDR2-1066
-# 4Gbit part, which whould amount to 1 GByte of memory in 2x32 or
-# 2GByte in 4x16 configuration.
+# 4 Gbit part
 class SimpleLPDDR2_S4(SimpleDRAM):
-    # Assuming 64 byte cache lines, use a 2kbyte page size, this
+    # Assuming 64 byte cache lines, use a 1kbyte page size, this
     # depends on the memory density
-    lines_per_rowbuffer = 32
+    lines_per_rowbuffer = 16
 
-    # Use two ranks
-    ranks_per_channel = 2
+    # Use a single rank
+    ranks_per_channel = 1
 
     # LPDDR2-S4 has 8 banks in all configurations
     banks_per_rank = 8
@@ -227,18 +226,19 @@
     # Pre-charge one bank 15 ns and all banks 18 ns
     tRP = '18ns'
 
-    # Assuming 64 byte cache lines, across a x64 interface (2x32 or
-    # 4x16), translates to BL8, 4 clocks @ 533 MHz
-    tBURST = '7.5ns'
+    # Assuming 64 byte cache lines, across a x32 DDR interface
+    # translates to two BL8, 8 clocks @ 533 MHz. Note that this is a
+    # simplification
+    tBURST = '15ns'
 
-    # LPDDR2-S4, 4 Gb
+    # LPDDR2-S4, 4 Gbit
     tRFC = '130ns'
     tREFI = '3.9us'
 
     # Irrespective of speed grade, tWTR is 7.5 ns
     tWTR = '7.5ns'
 
-    # Irrespective of size, tFAW is 50 ns
+    # Irrespective of density, tFAW is 50 ns
     tXAW = '50ns'
     activation_limit = 4
 
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