changeset fe54045c8670 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fe54045c8670
description:
mem: Add a LPDDR3-1600 configuration
This patch adds a typical (leaning towards fast) LPDDR3 configuration
based on publically available data. As expected, it looks very similar
to the LPDDR2-S4 configuration, only with a slightly lower burst time.
diffstat:
configs/common/MemConfig.py | 1 +
src/mem/SimpleDRAM.py | 38 ++++++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 0 deletions(-)
diffs (56 lines):
diff -r 5dd29a521cac -r fe54045c8670 configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Thu May 30 12:53:55 2013 -0400
+++ b/configs/common/MemConfig.py Thu May 30 12:53:56 2013 -0400
@@ -52,6 +52,7 @@
("simple_mem", "SimpleMemory"),
("ddr3-1600", "SimpleDDR3"),
("lpddr2_s4-1066", "SimpleLPDDR2_S4"),
+ ("lpddr3-1600", "SimpleLPDDR3"),
("wio-200", "SimpleWideIO"),
]
diff -r 5dd29a521cac -r fe54045c8670 src/mem/SimpleDRAM.py
--- a/src/mem/SimpleDRAM.py Thu May 30 12:53:55 2013 -0400
+++ b/src/mem/SimpleDRAM.py Thu May 30 12:53:56 2013 -0400
@@ -277,3 +277,41 @@
# Two instead of four activation window
tXAW = '50ns'
activation_limit = 2
+
+# High-level model of a single LPDDR3 x32 interface (one
+# command/address bus), with default timings based on a LPDDR3-1600 4
+# Gbit part
+class SimpleLPDDR3(SimpleDRAM):
+ # 4 Gb and 8 Gb devices use a 1 kByte page size, so ssuming 64 byte
+ # cache lines, that is 16 lines
+ lines_per_rowbuffer = 16
+
+ # Use a single rank
+ ranks_per_channel = 1
+
+ # LPDDR3 has 8 banks in all configurations
+ banks_per_rank = 8
+
+ # Fixed at 15 ns
+ tRCD = '15ns'
+
+ # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
+ tCL = '15ns'
+
+ # Pre-charge one bank 15 ns and all banks 18 ns
+ tRP = '18ns'
+
+ # Assuming 64 byte cache lines, across a x32 DDR interface
+ # translates to two bursts of BL8, 8 clocks @ 800 MHz
+ tBURST = '10ns'
+
+ # LPDDR3, 4 Gb
+ tRFC = '130ns'
+ tREFI = '3.9us'
+
+ # Irrespective of speed grade, tWTR is 7.5 ns
+ tWTR = '7.5ns'
+
+ # Irrespective of size, tFAW is 50 ns
+ tXAW = '50ns'
+ activation_limit = 4
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