> On April 18, 2013, 3:52 a.m., Andreas Hansson wrote: > > src/mem/coherent_bus.hh, line 134 > > <http://reviews.gem5.org/r/1826/diff/1/?file=35127#file35127line134> > > > > I'm not thrilled at how it's done at the moment, but I can see the need > > for something similar. > > > > I have quite some bus patches in the pipeline, I'll try and get them on > > the reviewboard early next week. > > Xiangyu Dong wrote: > before the bus patch release, I will leave it as is. > > Andreas Hansson wrote: > Great, I'll try and get those patches on the board next week. > > Thanks again for the very useful additions to the cache model.
Hi Andreas. I've updated this changeset to work with your new multi-layer bus model. - Xiangyu ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1826/#review4247 ----------------------------------------------------------- On May 30, 2013, 10:41 p.m., Xiangyu Dong wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1826/ > ----------------------------------------------------------- > > (Updated May 30, 2013, 10:41 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9639:2aae67c49743 > --------------------------- > mem: add retry mechanism for cache fills in classic cache model > The changeset 6122d201ff80 modeled the cache bank and blocks the cache access > if the target bank is busy. However, due to the lack of retry mechanism at > the > cache master port, that changeset cannot properly blocks the cache traffic > that > is towards CPU. > This patch modifies the CoherentBus model and adds a flow control scheme to > the > RespLayer. With this modification, cache fill operations can now be properly > modeled. > @todo The modification to CoherentBus is a little hacky. e.g. The recvRetry > functions for Req and Resp are not symmetric > @todo Might also need to modify noncoherent bus > @todo There is no write buffer entries for cache fill operations. An > incremental patch will be needed to model the cache fill buffer > > > Diffs > ----- > > src/mem/cache/base.hh e2fafd224f43 > src/mem/cache/cache_impl.hh e2fafd224f43 > src/mem/coherent_bus.hh e2fafd224f43 > src/mem/coherent_bus.cc e2fafd224f43 > > Diff: http://reviews.gem5.org/r/1826/diff/ > > > Testing > ------- > > > Thanks, > > Xiangyu Dong > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
