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(Updated July 18, 2013, 7:27 p.m.) Review request for Default. Repository: gem5 Description ------- Changeset 9627:6122d201ff80 --------------------------- mem: model data array bank in classic cache The classic cache does not model data array bank, i.e. if a read/write is being serviced by a cache bank, no other requests should be sent to this bank. This patch models a multi-bank cache. Features include: 1. detect if the bank interleave granularity is larger than cache line size 2. add CacheBank debug flag 3. Differentiate read and write latency 3a. read latency is still named as hit_latency 3b. write latency is named as write_latency 4. Add write_latency, num_banks, bank_itlv_bit into the Python parser Not modeled in this patch: Due to the lack of retry mechanism in the cache master port, the access form the memory side will not be denied if the bank is in service. Instead, the bank service time will be extended. This is equivalent to an infinite write buffer for cache fill operations. Diffs (updated) ----- configs/common/CacheConfig.py 761d680d7052 configs/common/Caches.py 761d680d7052 configs/common/Options.py 761d680d7052 src/mem/cache/BaseCache.py 761d680d7052 src/mem/cache/SConscript 761d680d7052 src/mem/cache/base.hh 761d680d7052 src/mem/cache/base.cc 761d680d7052 src/mem/cache/cache_impl.hh 761d680d7052 Diff: http://reviews.gem5.org/r/1809/diff/ Testing ------- Thanks, Xiangyu Dong _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
