On Wed, 31 Jul 2013, Steve Reinhardt wrote:
See for example this line, which is at http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l962: 962 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l962> flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 963 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l963> TheISA::NumFloatRegs + TheISA::NumIntRegs; So src_reg *was* offset by Ctrl_Base_DepTag, but now we're tweaking it to be offset by NumFloatRegs+NumIntRegs instead. For most ISAs this is a no-op, since Ctrl_Base_DepTag == (NumFloatRegs+NumIntRegs), but for ARM and x86 that's not the case. So now we have a situation where clearly sometimes it's expected to be adjusted by one offset, and sometimes by the other. The case for FP regs is a little more convoluted; if you look just a couple of lines above there, the code is: 956 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l956> src_reg = src_reg - TheISA::FP_Base_DepTag; 957 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l957> flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 958 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l958> DPRINTF(Rename, "Flattening index %d to %d.\n", 959 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l959> (int)src_reg, (int)flat_src_reg); 960 <http://repo.gem5.org/gem5/file/2492d7ccda7e/src/cpu/o3/rename_impl.hh#l960> flat_src_reg += TheISA::NumIntRegs; So again we're removing an offset of FP_Base_DepTag and then adding back an offset of NumIntRegs, though this time there's a flattening call in the middle. But again, if one expects that FP_Base_DepTag == NumIntRegs, it doesn't make sense to use different values in different places.
I initially thought you mean that we use different offsets in different parts of the code. But now it seems that you do not like the fact that in some ISAs FP_Base_DepTag == NumIntRegs and in some it is not true. Looking at the code for flattening register indices in src/arch/*/isa.hh, it seems that it is because of peculiarities of arm, sparc and x86 ISAs. I am guessing we have to live with it.
-- Nilay _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
